• 대한의용생체공학회:학술대회논문집
• /
• 대한의용생체공학회 1995년도 춘계학술대회
• /
• pp.155-159
• /
• 1995

A design method that can easily construct intelligent patient monitoring systems is proposed. To achieve the design method, the SES/MB concept and a discrete event-based logic control formalism based on a set theory is introduced. In this control paradigm the controller expects to receive confirming sensor responses to its control commands within definite time windows determined by DEVS model of the system under control. Because data to be used for rule-based symbolic reasoning are to be abstracted, several AI methods are applied the processes. These methods are applied to intelligent patient monitoring systems so that they facilitate transformation from low level raw data to high level linguistic data. Model-based system representations have advantages of reusability, extensibility, flexsibility, independent testability and encapsulation.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -3
• /
• pp.1972-1975
• /
• 2002

A new test approach based on a supply current test method is proposed for testing open faults in bipolar logic circuits. In the approach, only the open faults are detected by the supply current test method, which are difficult to be detected by functional test methods. The effectiveness of the approach is examined experimentally on open fault detection in TTL combinational circuits. The results shows that higher fault coverage can be established by applying a small number of test input vectors of the supply current test method after test vectors of functional test methods based on stuck-at models.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권1호
• /
• pp.71-78
• /
• 2013

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

• 한국정보처리학회:학술대회논문집
• /
• 한국정보처리학회 2003년도 춘계학술발표논문집 (하)
• /
• pp.1769-1772
• /
• 2003

소프트웨어 시험은 소프트웨어의 신뢰성을 직접적으로 향상시킬 수 있는 방법 중의 하나이지만 일반적으로 상당히 많은 비용이 드는 개발 과정이다. 따라서 경제적인 소프트웨어 개발을 위하여 소프트웨어 시험성을 강화시킬 수 있는 메커니즘들이 요구된다. 본 논문은 소프트웨어 시험성 강화 메커니즘들 중의 하나인 테스트 오러클의 생성을 지원하는 시험 환경의 구축 방법을 제안한다. 본 논문에서 제안하는 테스트 오러클 생성 지원 환경의 목적은 Statechart로 기술된 시험 대상 소프트웨어의 행위 모델로부터 실행 가능한 테스트 오러클의 생성을 지원하는 것이다.

• 대한전기학회논문지
• /
• 제43권3호
• /
• pp.504-514
• /
• 1994

Combinational automatic test pattern generators (CATPG) have already been commercialized because their algorithms are well known and practical, while sequential automatic test pattern generators(SATPG) have been regarded as impractical because they are computationally complex. A technique to use CATPG instead of SATPG for test generation of sequential circuits is proposed. Redesign of seauential circuits such as Level Sensitive Scan Design (LSSD) is inevitable to use CATPG. Various partial scan techniques has been proposed to avoid full scan such as LSSD. It ha sbeen reported that SATPG is required to use partial scan techniques. We propose a technique to use CATPG for a new partial scan technique, and propose a new CATPG algorithm for the partially scanned circuits. The partial scan technique can be another choice of design for testability because it is computationally advantageous.

• ETRI Journal
• /
• 제36권6호
• /
• pp.942-952
• /
• 2014

This paper presents a novel test point insertion (TPI) method for a pseudo-random built-in self-test (BIST) to reduce the area overhead. Recently, a new TPI method for BISTs was proposed that tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving control points. The replacement rule used in a previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip-flops. This paper proposes a logic cone analysis-based TPI approach to overcome the limitations. Logic cone analysis is performed to find candidate functional flop-flops for replacing dedicated flip-flops. Experimental results indicate that the proposed method reduces the test point area overhead significantly with minimal loss of testability by replacing the dedicated flip-flops.

• 전자공학회논문지C
• /
• 제35C권3호
• /
• pp.1-15
• /
• 1998

In this paper, we propose a partial scan test method which can be applied to large VLSI designs. In this method, it is not necessary to hold neither scanned nor unscanned flip-flops during scan in, test application,or scan out. This test method requires almost identical design for testability modification and test wave form when compared to the full scan test method, and the method is applicable to large VLSI chips. The well known FAN algorithm has been modified to devise to sequential ATPG algorithm which is effective for the proposed test method. In addition, a partial scan algorithm which is effective for the proposed test method. In addition, a partial algorithm determined a maximal set of flip-flops which gives high fault coverage when they are unselected. The experimental resutls show that the proposed method allow as large as 20% flip-flops to remain unscanned without much decrease in the full scan fault coverage.

• 반도체디스플레이기술학회지
• /
• 제19권2호
• /
• pp.82-87
• /
• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• 한국정보과학회:학술대회논문집
• /
• 한국정보과학회 2003년도 가을 학술발표논문집 Vol.30 No.2 (2)
• /
• pp.334-336
• /
• 2003

이 논문에서는 소프트웨어 프로젝트 수행 중에 비용이나 일정 측면에서 비중이 큰 테스트 작업의 위험도를 줄이기 위하여 테스트 가능성 검토 방법과 이를 객관적으로 측정하는 방법을 제시하였다. 막대한 예산이 소요되는 대규모 소프트웨어 프로젝트에서 정확한 ROI(Return of Investment)를 예측하고 테스트 작업에 걸림돌이 될만한 요소들을 파악한다면 소프트웨어 개발 작업이 더욱 효율적인 엔지니어링 작업이 될 것이다. 이 연구에서는 블랙박스 테스트의 기준이 되는 산출물들 중에 먼저 요구명세서의 테스트 가능성에 대한 검토 방법을 제시하였다. 사례연구를 통하여 요구명세서의 어떤 요소들이 테스트가능성을 높이는지 파악하였고 이를 항목으로 만들어 객관적인 측정이 가능하도록 하였다. 연구 결과는 테스트 작업에서 케이스 설계만이 아니라 테스트 실행, 결과의 분석, 결함 위치 발견 및 수정 작업까지도 비용을 줄여주는 효과를 보이고 있다.

• 한국정보처리학회논문지
• /
• 제6권3호
• /
• pp.766-772
• /
• 1999

With the increase of portable system and high-density IC, power consumption of VLSI circuits is very important factor in design process. Power estimation is required in order to estimate the power consumption. A simple and correct solution of power estimation is to use circuit simulation. But it is very time consuming and inefficient way. Probabilistic method has been proposed to overcome this problem. Transition density using probability was an efficient method to estimate power consumption using BDD and Boolean difference. But it is difficult to build the BDD and compute complex Boolean difference. In this paper, we proposed Propowest. Propowest is building a digraph of circuit, and easy and fast in computing transition density by using modified COP algorithm. Propowest provides an efficient way for power estimation.