• Journal of Applied Reliability
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• v.12 no.1
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• pp.47-56
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• 2012

Reliability demonstration tests with zero-failure acceptance criterion are most commonly used in the field of reliability application since they require fewer test samples and less test time compared to other test methods that guarantee the same reliability with a given confidence level. For products with lognormal lifetime distribution, an economic zero-failure test plan is developed that minimizes the total cost related to perform a life test to guarantee a specified reliability of a product with a given confidence level. A numerical example is provided to illustrate the use of the proposed test plan.

• The Journal of Information Systems
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• v.15 no.3
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• pp.107-129
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• 2006

The purpose of this study is to provide and validate an IT cost model hi which we link among cost center, cost object and flexible cost driver. in order to accomplish this purpose, this study utilizes ethnographic research methodology. At first we develop the cost model where the flexible cost driver is the distribution basis of overhead cost. For each cost driver, unit cost management model is also proposed. Then we employ the structured design methodology to validate the model. Based on the IT Cost requirements of a case company, the IT cost system was designed and developed for its test. The result shows the model we developed in this study is appropriate for managing IT resources and further, can be used as a reference model for calculating chargeback rates of other departments and IT budget of IT department.

• Journal of Applied Reliability
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• v.16 no.3
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• pp.238-244
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• 2016

Purpose: Domestic electric railway Regenerative Energy Storage System seriously affects the maintenance cost of the total operating expenses of nearly 60% of the total LCC (Life Cycle Cost) due to high dependence on foreign Leading company. Therefore by developing the system, it is important to lower the maintenance cost in the domestic supply. This study about the capacitor Reliability test and the purpose of this study is development electric railway Regenerative Energy Storage System. Methods: In case of, having a close relation between the temperature and the reaction rate, Accelerated Model was known that according to Arrhenius' law of chemical activity. If you apply this formula in using allowable temperature range of the capacitor can induce the Arrhenius empirical formula used in much Manufacture Fields. We evaluate the capacitors Leading company through the Arrhenius model. in order to providing a base for the localization of Ultra Capacitor. Conclusion: In this paper, we conducted a reliability test. And it was performed by the accelerated life test and Cycle Test with temperature and C-rate. and then MTBF and B10 life are estimated by analyzing the accelerated life test result. This is thought to need detailed study applying complex stress than about whether it matches the actual behavior in electric railway.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.137-140
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• 2000

In this paper, we have proposed an efficient test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph(STG)〔1〕 which is a kind of specification method for asynchronous circuits. To conduct a high-level test generation, we have defined a high-level fault model, called single State Transition Fault(STF) model on STG and proposed a test generation algorithm for STF model. The effectiveness of the proposed fault model and its test generation algorithm is shown by experimental results on a set of benchmarks given in the form of STG. Experimental results show that the generated test for the proposed fault model achieves high fault coverage over single input stuck-at fault model with low cost. We have also proposed extended STF model with additional gate-level information to achieve higher fault coverage in cost of longer execution time.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.140-148
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• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.6
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• pp.1138-1143
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• 2011

One of the critical items in radar testing is the ability to evaluate the performance of radar systems under real operational environments. But it takes lots of time and cost to operate real targets and analyze the test results due to a large amount of data based on these complicated environments. In this paper, the Radar Simulative T&E Lab. is introduced, and the test and analysis results of the developing radar for predicting the radar system performance are described in the Radar Simulative T&E Lab. This laboratory could be used to test the far-field characteristics of antenna radiation pattern and to perform an effective radar system test and evaluation using a simulative target generator under a low cost repeating test situation.

• Korea Journal of Hospital Management
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• v.26 no.1
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• pp.71-82
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• 2021

Purpose: The purpose of this study is to estimate incomes and costs of the medical clinics by using secondary data. Methodology: The medical incomes and costs were estimated from 405 clinics operated by sole practitioner providing out-patient services among all clinics subject to the Medical Cost Survey on National Health Insurance Patients in 2017, excluding dental clinics and oriental medical clinics. The incomes and costs of the medical clinics were reflected with incomes and costs of health insurance benefits and were calculated by types of medical services (i.e., basic care, surgery, general treatment, functional test, specimen test and imaging test). The costs were classified as follows: labor costs, equipment costs, material costs and overhead costs. Secondary data was used to estimate the incomes and costs of the medical clinics. For allocation bases for costs for each type of the medical service, the ratio of revenue from health insurance benefits by types of medical services was applied. However, labor costs were calculated with the activity ratio by types of medical services and occupations, using clinical expert panel data. Finding: The percentage of health insurance income for all medical income was 73.1%. The health insurance cost per clinic was 401,864 thousand won. Labor cost accounted for the largest portion of the health insurance income was 191,229 thousand won (47.6%), followed by management cost was 170,018 thousand won (42.3%), materials cost was 35,434 thousand won (8.8%), and equipment costs was 5,183 thousand won (1.3%). Practical Implications: This study suggests a method of estimating incomes and costs of medical clinic services by using secondary data. It could efficiently provide incomes and costs to assess an appropriate level of the health insurance fee to the clinics.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.60-67
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• 2013

Test cost reduction is necessary to test a complex System-on-a-Chip(SoC) which adopts various Intellectual Properties (IP). In this paper, test architecture with low pin count which is able to IP-based SoC test, using IEEE Std. 1149.7 and IEEE Std. 1500, is proposed. IEEE Std. 1500 provides independent access mechanism for each IP in IP-based SoC test. In this paper, just two test pins are required by composing that these independent access mechanism can be controlled by IEEE Std. 1149.7. The number of Chips which are tested at the same time is increased by reducing required test pin count at wafer and package level test, and consequently the overall manufacturing test cost will be reduced significantly.

• Magazine of the Korean Society of Agricultural Engineers
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• v.40 no.3
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• pp.35-41
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• 1998

Cost estimate system Will be changed from the prime. cost calculation to the historical cost data because the present system has some problems. In this situation, each owner should prepare his own cost estimate system based on the historical cost data. In this study, the standard work items were classified and the criteria of their work amount computation were established for rural improvement projects. And also the historical cost data were collected in all range of rural improvement projects, and the database system, "HICOMS" (HIstorical COst data Management System) was built. In order to test the applicability of the HICOMS, standard work cost and contractor cost were compared. The results by HICOMS showed high significance and it was concluded that the HICOMS could be applicable for the cost estimate of the rural improvement projects. projects.

• Journal of the Korean GEO-environmental Society
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• v.4 no.4
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• pp.73-84
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• 2003

In this study, the economic pile design procedure using the proof test results was proposed. In order to improve the inappropriate pile design routine, the proof test for 6 pile cases were performed and the construction saving effect were analyzed. The saving rate of construction cost with the small diameter piles and the large diameter drilled shafts were 34 - 47 and 0 - 55 %, respectively.