• 조명전기설비학회논문지
• /
• 제24권12호
• /
• pp.147-155
• /
• 2010

We studied on performance improvement of TTM(TI21 Test Meter) that is test and diagnosis devices for jointless audio frequency track circuit on Korean electric railway TI21 standard. Upgraded devices is AD-TTM(Advanced TI21 Test Meter). This can measure alternating frequency USB(Upper signal band) and LSB(Lower signal band). In the audio frequency track circuit, ${\pm}17[Hz]$ of nominal frequency are demodulated and supplied to track relay through AND gate. It is important that measurement function which is error between USB and LSB. Need of AD-TTM will stand out in the electric railway system because this is simple and accurate rather than the former device.

• 전자공학회논문지C
• /
• 제35C권6호
• /
• pp.48-55
• /
• 1998

본 논문에서는 테스트가 용이하도록 ECC(error checking circuit)를 내장하여 테스트를 수행할 수 있는 CAM(content addressable memory)를 설계하였다. 즉, CAM에서 발생하는 읽기, 쓰기 및 매치 동작의 기능 고장을 검사할 수 있는 회로를 내장한 CAM을 설계하였다. 일반적으로 테스트 회로를 내장하면 전체면적의 증가를 가져오게 된다. 본 논문에서는 기존의 병렬 비교기를 사용한 내장(built-in) 테스트 회로의 면적 오버헤드를 줄이기 위해서 새로 제안된 MTA 코드를 이용하였다. 설계한 회로는 VHDL 시뮬레이션을 통하여 검증하였으며, 0.B㎛ double-metal CMOS 공정을 이용하여 레이아웃을 수행하였다. ECC 회로의 경우 CAM의 기본 셀에서 매치기능을 담당하고 있는 XOR회로를 이용함으로써 약 30%정도 면적 감소를 가져왔다.

• 전자공학회논문지C
• /
• 제34C권8호
• /
• pp.49-63
• /
• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• ETRI Journal
• /
• 제28권2호
• /
• pp.182-190
• /
• 2006

The circuit modeling of interdigitated capacitors fabricated by high-k low-temperature co-fired ceramic (LTCC) sheets was investigated. The s-parameters of each test structure were measured from 50 MHz to 10 GHz, and the modeling was performed using these measured sparameters up to the first resonant frequency. Each test structure was divided into appropriate building blocks. The equivalent circuit of each building block was composed based on the partial element equivalent circuit (PEEC) method. Modeling was executed to optimize the parameters in the equivalent circuit of each building block. The validity of the extracted parameters was verified by the predictive modeling for the test structures with different geometry. After that, Monte Carlo analysis and sensitivity analysis were performed based on the extracted parameters. The modeling methodology can allow a device designer to improve the yield and to save time and cost for the design and manufacturing of devices.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
• /
• 제49권2호
• /
• pp.85-92
• /
• 2000

30 kVA rotating-field type Super-Conducting Generator is built and tested with intensive FE(Finite Element) analysis. The generator is driven by VVVF inverter-fed induction motor. Open Circuit Characteristic(OCC) and Short Circuit Characteristic(SCC) are presented in this paper. Also, the test result under the light load(up to 3.6 kW) are given. From the design stage, 2-D FE analysis coupled with the external circuit has been performed. The external circuit includes the end winding resistance and reactance as well as two dampers. When compared with the test data, the FE analysis results show a very good agreement.

• 대한전기학회논문지:시스템및제어부문D
• /
• 제49권6호
• /
• pp.322-329
• /
• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• 대한물리의학회지
• /
• 제5권2호
• /
• pp.193-201
• /
• 2010

Purpose : This study achieved to search the effect of the circuit exercise and conventional exercise on walking ability(walking speed, endurance, dynamic balance, speed, endurance and pedestrian crossing) in chronic stroke. Methods : Since is diagnosed by stroke, to 30 chronic stroke patients who more than 1 year past the 15 circuit exercise group, the 15 conventional exercise group random the circuit exercise group applied circuit exercise 3th 8 weeks each week after neurological treatment because assigning and the conventional exercise group executed round trip walk exercise in parallel bar 3th 8 weeks each week after neurological treatment. The data of 25 patients who complete experimental course were statistically analysed. Results : The results of this dissertation were as following : 1) There were significantly increased after experimental of 10 meter walk test, 6 minutes walk test and Timed "Up and Go" test in circuit exercise group (p<.001). 2) There were significantly increased after experimental of 2, 4 and 6 lane road crossing mobility in Walking circuit exercise group(p<.01). 3) There were significantly differences after experimental of 10 meter walk test, 6 minutes walk test and Timed "Up and Go" test change quantity between circuit exercise group and conventional exercise group(p<.05). 4) There were correlations were found between the TUG test and 2, 4 and 6 lane road (2 lane road; r=.463, p<.01., 4 lane road; r=515, p<.01., 6lane road; r=.710, p<.01), and there were correlations were found between the 10 meter walk test and 6 minutes walk test(r=.595, p<.01), TUG test(r=.662, p<.01) and 6 lane road(r=.527, p<.01). Conclusion : Even if improvement of walk function through training consists in room, transfer of actuality pedestrian crossing is no change outside the room. Because it is much variable of the weather, seasonal factor, temperature, pedestrian number, state of underneath etc. outside the room. Then, in room after direction promotion of walk function to be promotion of walk function in actuality life and need development of connectable training method consider.

• The Journal of the Acoustical Society of Korea
• /
• 제20권1E호
• /
• pp.14-19
• /
• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• 전자공학회논문지C
• /
• 제35C권4호
• /
• pp.30-37
• /
• 1998

In this paper, we propose a test generation method for large scale sequential circuits based on circuit partitioning to increase the size of circuits that the implicit product machine traversal (IPMT) method can handle. Our method paratitions a circuit under test into subset circuits with only single output, and performs a partial scan design using the state transtition cost that represents a degree of the connectivity of the subset circuit. The IPMT method is applied to the partitioned partial scan circuits in test generation. Experimental results for ISCAS89 benchmark circuits with more thatn 50 flip-flops show that our method has generated test patterns with almost 100% fault coverage at high speed by use of 34%-73% scanned flip-flops.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 추계학술대회 논문집 전기물성,응용부문
• /
• pp.160-163
• /
• 2003

This paper represent a test method for the reliability assessment on the indoor vacuum circuit breakers used in the distribution system by an accelerated life test. In order to guarantee the lifetime in service of the vacuum circuit breaker, additional test methods are suggested. Multiple closing-opening operation test under no load condition as a mechanical endurance test and a check of the quality in the vacuum interrupter are adopted to assure the long-term reliability of the vacuum circuit breaker.