• Title/Summary/Keyword: test algorithm

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The Supply Water Algorithm for a Condensing Gas Boiler Control (콘덴싱가스보일러 제어를 위한 공급수알고리즘)

  • Han, Do-Young;Yoo, Byeong-Kang
    • Korean Journal of Air-Conditioning and Refrigeration Engineering
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    • v.23 no.6
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    • pp.441-448
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    • 2011
  • The energy consumption of a condensing gas boiler may be greatly reduced by the effective operation of the unit. In this study, the supply water algorithm for a condensing gas boiler control was developed by using the fuzzy logic. This includes the supply water set temperature algorithm, and the control algorithms of a gas valve, a blower and a pump. For the set temperature algorithm, the outside air temperature and the return water temperature were used as input variables. The supply water temperature difference and its slope were used as input variables of the gas valve and blower control algorithm. And the supply water temperature and the return water temperature were used as input variables of the pump control algorithm. In order to analyse performances of these algorithms, the dynamic model of a condensing gas boiler was used. The initial start-up test, the supply water set temperature change test, the outside air temperature change test, and the return water temperature change test were performed. Simulation results showed that algorithms developed in this study may be practically applied for the effective control of a condensing gas boiler.

Efficient Path Delay Test Generation for Custom Designs

  • Kang, Sung-Ho;Underwood, Bill;Law, Wai-On;Konuk, Haluk
    • ETRI Journal
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    • v.23 no.3
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    • pp.138-149
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    • 2001
  • Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

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Generating Test Cases of Simulink/Stateflow Model Based on RRT Algorithm Using Heuristic Input Analysis (휴리스틱 입력 분석을 이용한 RRT 기반의 Simulink/Stateflow 모델 테스트 케이스 생성 기법)

  • Park, Hyeon Sang;Choi, Kyung Hee;Chung, Ki Hyun
    • KIPS Transactions on Software and Data Engineering
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    • v.2 no.12
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    • pp.829-840
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    • 2013
  • This paper proposes a modified RRT (Rapidly exploring Random Tree) algorithm utilizing a heuristic input analysis and suggests a test case generation method from Simulink/Stateflow model using the proposed RRT algorithm. Though the typical RRT algorithm is an efficient method to solve the reachability problem to definitely be resolved for generating test cases of model in a black box manner, it has a drawback, an inefficiency of test case generation that comes from generating random inputs without considering the internal states and the test targets of model. The proposed test case generation method increases efficiency of test case generation by analyzing the test targets to be satisfied at the current state and heuristically deciding the inputs of model based on the analysis during expanding an RRT, while maintaining the merit of RRT algorithm. The proposed method is evaluated with the models of ECUs embedded in a commercial passenger's car. The performance is compared with that of the typical RRT algorithm.

Solving the test resource allocation using variable group genetic algorithm (가변 그룹 유전자알고리즘 기반의 시험자원할당 문제 해결)

  • Mun, Chang-min
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.8
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    • pp.1415-1421
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    • 2016
  • There are considerable concern on the methods for the efficient utilization of the test-resources as increasing of the number of the tests for functionality and performance verification of weapon systems. Furthermore, with an increase in the complexity of the resource assignment the decision support is required. Test resource allocation is basically the same problems as conventional NP-hard FJSP(Flexible Job Shop Problem), therefore empirical test resource allocation method that has been used in many decades is limited in the time performance. Although research has been conducted applying the genetic algorithm to the FJSP, it is limited in the test resource allocation domain in which more than one machine is necessary for a single operation. In this paper, a variable group genetic algorithm is proposed. The algorithm is expected to improve the test plan efficiency by automating and optimizing the existing manual based allocation. The simulation result shows that the algorithm could be applicable to the test plan.

Development Process of FPGA-based Departure from Nucleate Boiling Ratio Algorithm Using Systems Engineering Approach

  • Hwang, In Sok;Jung, Jae Cheon
    • Journal of the Korean Society of Systems Engineering
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    • v.14 no.2
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    • pp.41-48
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    • 2018
  • This paper describes the systems engineering development process for the Departure from Nucleate Boiling Ratio (DNBR) algorithm using FPGA. Current Core Protection Calculator System (CPCS) requirement and DNBR logic are analyzed in the reverse engineering phase and the new FPGA based DNBR algorithm is designed in the re-engineering phase. FPGA based DNBR algorithm is developed by VHSIC Hardware Description Language (VHDL) in the implementation phase and VHDL DNBR software is verified in the software Verification & Validation phase. Test cases are developed to perform the software module test for VHDL software modules. The APR 1400 simulator is used to collect the inputs data in 100%, 75%, and 50% reactor power condition. Test input signals are injected to the software modules following test case tables and output signals are compared with the expected test value. Minimum DNBR value from developed DNBR algorithm is validated by KEPCO E&C CPCS development facility. This paper summarizes the process to develop the FPGA-based DNBR calculation algorithm using systems engineering approach.

Performance Advancement of Evaluation Algorithm for Inner Defects in Semiconductor Packages (반도체 패키지 내부결함 평가 알고리즘의 성능 향상)

  • Kim, Chang-Hyun;Hong, Sung-Hun;Kim, Jae-Yeol
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.15 no.6
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    • pp.82-87
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    • 2006
  • Availability of defect test algorithm that recognizes exact and standardized defect information in order to fundamentally resolve generated defects in industrial sites by giving artificial intelligence to SAT(Scanning Acoustic Tomograph), which previously depended on operator's decision, to find various defect information in a semiconductor package, to decide defect pattern, to reduce personal errors and then to standardize the test process was verified. In order to apply the algorithm to the lately emerging Neural Network theory, various weights were used to derive results for performance advancement plans of the defect test algorithm that promises excellent field applicability.

Compressor Control of a Multi-type AIr Conditioning System (멀티형 냉방시스템의 압축기 제어)

  • 한도영;권형진
    • Korean Journal of Air-Conditioning and Refrigeration Engineering
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    • v.13 no.8
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    • pp.780-786
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    • 2001
  • For the compressor speed control of a multi-type air conditioning system, a fuzzy control algorithm was developed. The sum of zone temperature errors and its derivative were used as input variables, and the compressor speed was selected as the output variable. To test the effectiveness of the control algorithm, one outdoor environmental chamber and four indoor environmental chambers were used. In the chambers the zone temperature step change test and the indoor unit change over test were performed. Test results showed that, for the control of compressor speed, the fuzzy control algorithm was more effective than the conventional proportional control algorithm for the energy conservation.

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Development of Algorithm of Surge Test for Quality Control on Electrical Parts of Throttle Body in Automobiles (차량 드로틀 보디 전장부품의 품질관리 성능시험 알고리즘 개발)

  • Son, Jae-Hwan;Kim, Tae-Han
    • Journal of the Korean Society of Industry Convergence
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    • v.9 no.1
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    • pp.67-72
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    • 2006
  • This study is on the development of algorithm of surge test for quality control on electrical parts of throttle body in automobiles with internal combustion engine, not only to know its condition to be good or not, but also jugding its condition to be classified into six types. To know whether its condition to be good or not, comparing and analyzing between two waveforms generated from master and test coil of throttle body. If test net area is below 20% of master area, the condition of test coil is good. By analyzing test coil waveform to master coil waveform, the condition of test coil into winding badness, insulation badness, layer and corona discharge, short badness should known. Therefore quality control system on electrical parts of throttle body should be developed.

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A Test Algorithm for Data Processing Function of MC68000 ${\mu}$ P (MC68000 ${\mu}$ P의 데이터 처리기능에 관한 시험 알고리즘)

  • Kim, Jong Hoon;Ahn, Gwang Seon
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.2
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    • pp.197-205
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    • 1986
  • In this paper, we present an efficient test algorithm for data processing function of MC68000 \ulcorner. The test vector for functional testing is determined by stuck-at, coupling and transition fault for data storage and transfer. But for data manipulation it is determined by a boolean function of micro-operation. This test algorithm is composed of 3 parts, choosing optimum test instructions for maximizing fault coverage and minimizing test process time, deciding the test order for minimizing test ambiguity, and processing the actual test.

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Character Recognition Algorithm using Accumulation Mask

  • Yoo, Suk Won
    • International Journal of Advanced Culture Technology
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    • v.6 no.2
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    • pp.123-128
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    • 2018
  • Learning data is composed of 100 characters with 10 different fonts, and test data is composed of 10 characters with a new font that is not used for the learning data. In order to consider the variety of learning data with several different fonts, 10 learning masks are constructed by accumulating pixel values of same characters with 10 different fonts. This process eliminates minute difference of characters with different fonts. After finding maximum values of learning masks, test data is expanded by multiplying these maximum values to the test data. The algorithm calculates sum of differences of two corresponding pixel values of the expanded test data and the learning masks. The learning mask with the smallest value among these 10 calculated sums is selected as the result of the recognition process for the test data. The proposed algorithm can recognize various types of fonts, and the learning data can be modified easily by adding a new font. Also, the recognition process is easy to understand, and the algorithm makes satisfactory results for character recognition.