• Research in Mathematical Education
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• v.12 no.1
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• pp.27-37
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• 2008

A test as a form of diagnostic of algorithm and logic abilities is considered. Such test for measuring abilities and achievements of talented children has been designed and used at the Kharkiv Regional Olympiad in Informatics. Quality of the test and its items is analyzed. Correlation between the test results of children and their success in creating mathematical models, designing of complicated algorithms and translating these algorithms into computer programs is discussed.

• Journal of the Korea Institute of Military Science and Technology
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• v.23 no.3
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• pp.221-228
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• 2020

This paper presents the radar counter jamming algorithm and ground far-field test results for the pull-off deceptive jamming signals like RGPO(Range Gate Pull Off) and VGPO(Velocity Gate Pull Off). We designed the radar counter jamming algorithm according to the characteristics of the deceptive jamming signals. This algorithm is validated by simulation before ground far-field test. The existing X-band AESA radar demonstrator was used to test the proposed algorithm. The proposed algorithm was applied to the radar processor software. The deceptive jamming signals generated using the commercial jamming signal generator. We performed the repeated ground far-field test with the test scenario. Test results show that the proposed counter deceptive jamming algorithm works in the real radar system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.1-15
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• 1998

In this paper, we propose a partial scan test method which can be applied to large VLSI designs. In this method, it is not necessary to hold neither scanned nor unscanned flip-flops during scan in, test application,or scan out. This test method requires almost identical design for testability modification and test wave form when compared to the full scan test method, and the method is applicable to large VLSI chips. The well known FAN algorithm has been modified to devise to sequential ATPG algorithm which is effective for the proposed test method. In addition, a partial scan algorithm which is effective for the proposed test method. In addition, a partial algorithm determined a maximal set of flip-flops which gives high fault coverage when they are unselected. The experimental resutls show that the proposed method allow as large as 20% flip-flops to remain unscanned without much decrease in the full scan fault coverage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.14-22
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• 2016

Because fuses have many parts, human error can occur during visual inspections. This paper proposes an automatic ammunition test algorithm for preventing human error during an inspection. The automatic ammunition test algorithm consists of the following three steps. First, the image input and preprocessing step is where an inspection image is rotated using an image rotation algorithm and the image is converted to a binary image. Second, the inspection step of arming determines if the ammunition is armed using Masked Template Matching algorithm, etc. Third, the inspection step of the parts determines if the parts are omitted using an image searching algorithm, etc. The arming or parts omission of the fuse are detected efficiently using the ammunition automatic test algorithm. The ammunition automatic test algorithm is expected to help improve the safety and reliability of 40 mm grenade fuse.

• ETRI Journal
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• v.17 no.3
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• pp.45-63
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• 1995

This paper proposes an algorithm to improve the correlation between giga-hertz transverse electromagnetic (GTEM) cell and open area test site (OATS). It is based on the dipole modeling process of an unknown source object in a GTEM cell and on the evaluation of the approximate far field equations correlated with measured GTEM powers at output port of the GTEM cell. In this algorithm, the relative phase differences between dipole moments play an important part in modeling the test object as a set of dipoles and offer stable calculation of emission values. The radiated emission test using this algorithm requires fifteen orientations of equipment under test, but the increased orientations as compared with the previous method have little effect on the time needed for testing. Radiation from a notebook computer has been tested for statistical analysis of the correlation between GTEM data and OATS data. The emission test results of the notebook computer show that the mean, the standard deviation, and the correlation coefficient are -0.62, 1.99, and +0.85, respectively. These figures indicate that this algorithm provides improved accuracy in the measurement of electromagnetic emissions over the previous method.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2015.11a
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• pp.185-186
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• 2015

The Standard penetration test determines the type of soil according to soil bearing capacity, and this classifies the subsoil into many layers. Construction project managers are willing to know the depth of the present types of subsoil on site in order to make plans on earthwork stage during excavation. However the standard penetration test may not provide accurate information on subsoil type due to incorrect spacing. To solve this problem, this study propose a conceptual algorithm for determining the spacing of standard penetration test spots to essentially tests relevant locations on which to be applied the standard penetration test. This provides the acquirement of the accurate layered model volume of earthwork revised into geological columnar section. This algorithm will determine the appropriate standard penetration test spots spacing on a given size of site to optimize the accuracy of the earthwork volume, time and cost.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.140-148
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• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.

• ETRI Journal
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• v.31 no.2
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• pp.209-214
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• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1193-1199
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• 1996

This paper introduces an algorithm which uses MUIO and the shortest paths to minimize the length of test sequence. The length of test sequence is equal to the total number of the edges in a symmetric test graph $G^{*}$. Therefore, it is important to make a $G^{*}$ with the least number of the edges. This algorithm is based on the one proposed Shen[2]. It needs the complexity to make shortest paths but reduces the thest sequence by 1.0~9.8% over the Shen's algorithm. and this technique, directly, derives a symmetric test graph from an FMS.

• Journal of the Korean Operations Research and Management Science Society
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• v.42 no.3
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• pp.13-24
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• 2017

This paper aims to implement "structural changes detection procedure" in pairs trading algorithm and to show that the proposed approach outperforms the extant pair trading algorithm. Structural changes in pairs trading are defined in terms of changes in cointegrating factors and broken cointegration relationship. These changes are designed to test extant structural changes and unit root test methodologies. The simulation finds that expanding the changes in structure, increasing the mean reverting process of spread, and extending the consecutive days of broken cointegration will increase the performances of the proposed algorithm. Empirical study results are also consistent those of the simulation studies. The proposed algorithm outperforms the extant algorithm relative to risk and return given that the cumulative profit/loss has a significant upward-slope with minimal variance.