• 한국통신학회논문지
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• 제22권7호
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• pp.1394-1402
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• 1997

In this work, an efficient test algorithm and BIST architeture a for embedded memories are presented. The proposed test algorithm can fully detect stuck-at fault, transition fault, coupling fault. Moreover, the proposed test algorithm can detect nighborhood pattern sensitive fault which could not be detected in previous march test algoarithms. The proposed test algorithm perposed test algorithm performs testing for neghborhood pattern sensitive fault using backgroung data which has been used word-oriented memory testing.

• Journal of Advanced Marine Engineering and Technology
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• 제22권5호
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• pp.687-692
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• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.

• ETRI Journal
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• 제28권4호
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• 전자공학회논문지A
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• 제30A권2호
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

• ETRI Journal
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• 제30권4호
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• pp.555-564
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• 2008

This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual-port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual-port memories.

• 한국신뢰성학회지:신뢰성응용연구
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• 제18권3호
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• pp.229-239
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• 2018

Purpose: There is a difficulty in Environmental Stress Screening (ESS) test design for weapon system's electrical/electronic components/products in small and medium-sized enterprises. To overcome this difficulty, I propose an easy ESS test design approach algorithm that is optimized with only one environment tolerance design information parameter (${\Delta}T$). Methods: To propose the mass production weapon system ESS test design for cost-effective optimization, I define an optimum cost-effective mathematical model ESS test algorithm model based on modified MIL-HDBK-344, MIL-HDBK-2164 and DTIC Technical Report 2477. Results: I clearly confirmed and obtained the quantitative data of ESS effectiveness and cost optimization along our ESS test design algorithm through the practical case. I will expect that proposed ESS test method is used for ESS process improvement activity and cost cutting of mass production weapon system manufacturing cost in small and medium-sized enterprises. Conclusion: In order to compare the effectiveness of the proposed algorithm, I compared the effectiveness of the existing ESS test and the proposed algorithm ESS test based on the existing weapon system circuit card assembly for signal processing. As a result of the comparison, it was confirmed that the test time was reduced from 573.0 minutes to 517.2minutes (9.74% less than existing test time).

• 한국멀티미디어학회논문지
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• 제10권7호
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• pp.912-922
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• 2007

원격교육 시스템의 평가 시스템에서 평가의 공정성을 위하여 매 평가 시 평가지의 난이도를 일정하게 유지할 수 있는 방법이 요구된다. 본 논문에서는 유전자 알고리즘 기반의 평가지 생성 알고리즘을 제안한다. 평가지의 각 문항에 대한 난이도가 제출자에 의해서 지정되는 기존의 방법과는 달리 제안한 알고리즘에서는 각 문항의 난이도가 학생들의 평가 결과에 따라 적응적으로 조절되고, 평가지의 평균 난이도를 일정한 수준으로 유지할 수 있다. 제안한 알고리즘에서는 평가지에 동일한 문항이 중복으로 포함되는 것을 배제하고, 이전 평가의 결과를 반영하여 적응적으로 난이도가 조절될 수 있는 새로운 형태의 유전 연산자를 설계하고 구현한다. 그리고 모의실험을 통해 기존의 임의선택 방법과 모의 담금질 방법에 비해 균일한 난이도를 갖는 평가지가 생성될 수 있음을 보인다.

• 반도체디스플레이기술학회지
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• 제3권4호
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• pp.19-27
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• 2004

The characteristic evaluation of A/D converter is to measure the linearity of the converter. The evaluation of the linearity is to measure the DNL, INL, gain error and offset error in the various test parameters of A/D converter. Generally, DNL and INL are to be measured by the Histogram Test Algorithm in the DSP-based ATE environment. And gain error and offset error are to be measured by the calculation equation of the measuring algorithm. It is to propose the new Concurrent Histogram Test Algorithm for the test of the housekeeping A/D converter used in the CDMA cellular phone. Using the proposed method, it is to measure the DNL, INL, gain error and offset error concurrently and to show the measured results.

• 전자공학회논문지A
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• 제29A권11호
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• pp.62-69
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• 1992

In this paper, a measurement system of surface flatness test using 2-Bucket algorithm phase-shifting interferometry is designed and constructed. In the conventional surface flatness test system using phase shifting interferometry, it is needed more than 3 fringe datas but we propose 2-Bucket algorithm phase-shifting interferometry which only uses two fringe datas. 2-Bucket algorithm uses the relative phase differences of the neighbour pixels. If we watch the result of phase-shift error test simulation, 2-Bucket algorithm has the same calculating values that 3-Bucket, 4-Bucket and 5-Bucket algorithm have them. Experiments have been carried out on the silicon wafer. The measurement of silicon wafer's surface flatness shows that the flatness topography using 2-Bucket algorithm is similar to that of other algorithms.

• 한국컴퓨터정보학회논문지
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• 제25권9호
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• pp.193-201
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• 2020

본 연구에서는 Test-and-Set 알고리즘을 수행하는 시뮬레이션 앱을 개발하였다. Test-and-Set 알고리즘은 고난이도 알고리즘이라 이를 이해하기 어려워하는 학습자들을 위하여 이 시뮬레이션 앱을 만들었다. 본 시뮬레이션 앱을 이용하여 Test-and-Set 알고리즘의 이해를 원하는 학습자들이 모여 팀을 이루고 논의하며 실습을 할 수 있도록 하였으며, 이런 여러 팀들이 동시에 실습할 수 있도록 만들었다. 구성한 시뮬레이션 앱에서 기계어 명령어라고 가정한 Test-and-Set 명령어를 큐를 이용하여 인터럽트 받지 않게 구성하였으며, 임계영역 문제에서 해결해야 하는 '상호배제', '진행', '제한된 대기'의 3조건이 모두 잘 수행됨을 볼 수 있었다.