• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1394-1402
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• 1997

In this work, an efficient test algorithm and BIST architeture a for embedded memories are presented. The proposed test algorithm can fully detect stuck-at fault, transition fault, coupling fault. Moreover, the proposed test algorithm can detect nighborhood pattern sensitive fault which could not be detected in previous march test algoarithms. The proposed test algorithm perposed test algorithm performs testing for neghborhood pattern sensitive fault using backgroung data which has been used word-oriented memory testing.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.5
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• pp.687-692
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• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.

• ETRI Journal
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• v.28 no.4
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

• ETRI Journal
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• v.30 no.4
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• pp.555-564
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• 2008

This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual-port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual-port memories.

• Journal of Applied Reliability
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• v.18 no.3
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• pp.229-239
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• 2018

Purpose: There is a difficulty in Environmental Stress Screening (ESS) test design for weapon system's electrical/electronic components/products in small and medium-sized enterprises. To overcome this difficulty, I propose an easy ESS test design approach algorithm that is optimized with only one environment tolerance design information parameter (${\Delta}T$). Methods: To propose the mass production weapon system ESS test design for cost-effective optimization, I define an optimum cost-effective mathematical model ESS test algorithm model based on modified MIL-HDBK-344, MIL-HDBK-2164 and DTIC Technical Report 2477. Results: I clearly confirmed and obtained the quantitative data of ESS effectiveness and cost optimization along our ESS test design algorithm through the practical case. I will expect that proposed ESS test method is used for ESS process improvement activity and cost cutting of mass production weapon system manufacturing cost in small and medium-sized enterprises. Conclusion: In order to compare the effectiveness of the proposed algorithm, I compared the effectiveness of the existing ESS test and the proposed algorithm ESS test based on the existing weapon system circuit card assembly for signal processing. As a result of the comparison, it was confirmed that the test time was reduced from 573.0 minutes to 517.2minutes (9.74% less than existing test time).

• Journal of Korea Multimedia Society
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• v.10 no.7
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• pp.912-922
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• 2007

Evaluation of distance teaming systems needs a method that maintains a consistent level of difficulty for each test. In this paper, we propose a new algorithm for test sheet generation based on genetic algorithm. Unlike the existing methods that difficulty of each test item is assigned by tutors, in the proposed method, that can be adjusted by the result of the previous tests and the average difficulty of test sheet can be consistently reserved. We propose the new genetic operators to prevent duplications of test items in a test sheet and apply the adjusted difficulty of each test item. The result of simulation shows that difficulty of the test sheet generated by proposed method can be more regular than the random method and the simulated annealing method.

• Journal of the Semiconductor & Display Technology
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• v.3 no.4
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• pp.19-27
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• 2004

The characteristic evaluation of A/D converter is to measure the linearity of the converter. The evaluation of the linearity is to measure the DNL, INL, gain error and offset error in the various test parameters of A/D converter. Generally, DNL and INL are to be measured by the Histogram Test Algorithm in the DSP-based ATE environment. And gain error and offset error are to be measured by the calculation equation of the measuring algorithm. It is to propose the new Concurrent Histogram Test Algorithm for the test of the housekeeping A/D converter used in the CDMA cellular phone. Using the proposed method, it is to measure the DNL, INL, gain error and offset error concurrently and to show the measured results.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.11
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• pp.62-69
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• 1992

In this paper, a measurement system of surface flatness test using 2-Bucket algorithm phase-shifting interferometry is designed and constructed. In the conventional surface flatness test system using phase shifting interferometry, it is needed more than 3 fringe datas but we propose 2-Bucket algorithm phase-shifting interferometry which only uses two fringe datas. 2-Bucket algorithm uses the relative phase differences of the neighbour pixels. If we watch the result of phase-shift error test simulation, 2-Bucket algorithm has the same calculating values that 3-Bucket, 4-Bucket and 5-Bucket algorithm have them. Experiments have been carried out on the silicon wafer. The measurement of silicon wafer's surface flatness shows that the flatness topography using 2-Bucket algorithm is similar to that of other algorithms.

• Journal of the Korea Society of Computer and Information
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• v.25 no.9
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• pp.193-201
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• 2020

In this study, we developed a simulation app that performs the Test-and-Set algorithm. The test-and-set algorithm is a highly difficult algorithm, so this simulation app was created for learners who have difficulty understanding it. Learners who want to understand the Test-and-Set algorithm gather to form a team, and use this simulation app to discuss and practice, and these teams can practice at the same time. The test-and-set, which is assumed to be a machine language, is not interrupted by using a queue, and it can be seen that the configured simulation app performs well in all three conditions of 'mutual exclusion', 'progress', and 'bounded waiting' that must be solved in the critical area problem.