• Solar Energy
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• v.12 no.2
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• pp.62-78
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• 1992

The solar cells of $ITO_{(n)}/Si_{(p)}$, which are ITO thin films deposited and heated on Si wafer 190[$^{\circ}C$], were fabricated by two source vaccum deposition method, and their electrical properties were investigated. Its maximum output is obtained when the com- position of the thin film consist of indium oxide 91[mole %] and thin oxide 9[mole %]. The cell characteristics can be improved by annealing but are deteriorated at temperature above 600[$^{\circ}C$] for longer than 15[min]. Also, we investigated the spectral response with short circuit current of the cells and found that the increasing of the annealing caused the peak shifted to the long wavelength region. And by experiment of the X-ray diffraction, it is shown to grow the grains of the thin film with increasment of annealing temperature. The test results from the $ITO_{(n)}/Si_{(p)}$ solar cell are as follows. short circuit current : Isc= 31 $[mW/cm^2]$ open circuit voltage : Voc= 460[mV] fill factor : FF=0.71 conversion efficiency : ${\eta}$=11[%]. under the solar energy illumination of $100[mW/cm^2]$.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.449-449
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• 2011

We reported the direct effect of intrinsic surface energy of dry adhesive material to the Van der Waals and capillary forces contributions of the total adhesion force in an artificial gecko-inspired adhesion system. To mimic the gecko foot we fabricated tilted nanohairy structures using both lithography and ion beam treatment. The nanohairy structures were replicated from Si wafer mold using UV curable polymeric materials. The control of nanohairs slanting angles was based on the uniform linear argon ion irradiation to the nanohairy polymeric surface. The surface energy was studied utilizing subsequent conventional oxygen ion treatment on the nanohairy structures which resulted in gradient surface energy. Our shear adhesion test results were found in good agreement with the accepted Van der Waals and capillary forces theory in the gecko adhesion system. Surface energy would give a direct impact to the effective Hamaker constant in Van der Waals force and the filling angle (${\varphi}$) of water meniscus in capillary force contributions of gecko inspired adhesion system. With the increasing surface energy, the effective Hamaker constant also increased but the filling angle decreased, resulting in a competition between the two forces. Using a simple mathematical model, we compared our experimental results to show the quantitative contributions of Van der Waals and capillary forces in a single adhesion system on both hydrophobic and hydrophilic surfaces. We found that the Van der Waals force contributes about 82.75% and 89.97% to the total adhesion force on hydrophilic and hydrophobic test surfaces, respectively, while the remaining contribution was occupied by capillary force. We also showed that it is possible to design ultrahigh dry adhesive with adhesion strength of more than 10 times higher than apparent gecko adhesion force by controlling the surface energy and the slanting angle induced-contact line of dry adhesive the materials.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.123-123
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• 2012

최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.

• Journal of the Korean Society for Heat Treatment
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• v.22 no.5
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• pp.267-274
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• 2009

Titanium Chromium Nitrided (TiCrN) coatings were deposited on stainless steel 316 L and Si (100) wafer by inductively coupled plasma assisted D.C. magnetron sputtering at the various sputtering power on Cr target and $N_2/Ar$ gas ratio. Increasing the sputtering power of Cr target, XRD patterns were changed from TiCrN to nitride $Cr_2Ti$. The maximum hardness was $Hk_{3g}$ 3900 at $0.3\;N_2/Ar$ gas ratio. The thickness of the TiCrN films increased as the Cr target power increased, and it showed over $Hk_{5g}3100$ hardness at 100 W, 150 W. TiCrN films were deposited by the ICP assisted DC magnetron sputtering shown good wear resistance as the $N_2/Ar$ gas ratio was 0.1, 0.3.

• Journal of Astronomy and Space Sciences
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• v.21 no.4
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• pp.481-492
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• 2004

We report the successful fabrication and I-V curve superconductivity test results of the Nb/Al-based superconducting tunnel junctions. STJs with side-lengths of 20, 40, 60 and $80{\mu}m$ were fabricated by deposition of polycrystalline Nb/Al/AlOx/Al/Nb 5-layer thin films incorporated on a 3-inch Si wafer. STJ was designed by $Tanner^{TM}$ L-Edit 8.3 program, and fabricated in SQUID fabrication facility, KRISS. S-layer STJ thin-films were fabricated using UV photolithography, DC magnetron sputtering, Reactive ion etching, and CVD(Chemical Vapor Deposition) techniques. Superconducting state test for STJ was succeeded in 4K with liquid helium cooling system. Their performance indicators such ie energy gap, normal resistance, normal resistivity, dynamic resistance, dynamic resistivity, and quality factor were measured from I-V curve. Fabricated Nb/Al STJ shows $11\%$ higher FWHM energy resolution than genuine Nb STJ.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.