• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.529-529
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• 2006

Several laboratories worldwide have demonstrated the feasibility of producing amorphous silicon thin film transistor (TFT) arrays at temperatures that are sufficiently low to be compatible with flexible foils such as stainless steel or high temperature polyester. These arrays can be used to fabricate flexible high information content display prototypes using a variety of different display technologies. However, several questions must be addressed before this technology can be used for the economic commercial production of displays. These include process optimization and scale-up to address intrinsic electrical instabilities exhibited by these kinds of transistor device, and the development of appropriate techniques for the handling of flexible substrate materials with large coefficients of thermal expansion. The Flexible Display Center at Arizona State University was established in 2004 as a collaboration among industry, a number of Universities, and US Government research laboratories to focus on these issues. The goal of the FDC is to investigate the manufacturing of flexible TFT technology in order to accelerate the commercialization of flexible displays. This presentation will give a brief outline of the FDC's organization and capabilities, and review the status of efforts to fabricate amorphous silicon TFT arrays on flexible foils using a low temperature process. Together with industrial partners, these arrays are being integrated with cholesteric liquid crystal panels, electrophoretic inks, or organic electroluminescent devices to make flexible display prototypes. In addition to an overview of device stability issues, the presentation will include a discussion of challenges peculiar to the use of flexible substrates. A technique has been developed for temporarily bonding flexible substrates to rigid carrier plates so that they may be processed using conventional flat panel display manufacturing equipment. In addition, custom photolithographic equipment has been developed which permits the dynamic compensation of substrate distortions which accumulate at various process steps.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.458-461
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• 2015

In this paper 2 types of voltage references and a current reference suitable for low-voltage, low-power circuits are proposed and designed with $0.35{\mu}m\;CMOS$ process. MOS transistors operating in weak inversion and bulk-driven technique are utilized to achieve low-voltage and low-power features. The first voltage reference consumes 1.43uA from a supply voltage of 1.2V while it has a reference voltage of 585mV and a TC(Temperature Coefficient) of $6ppm/^{\circ}C$. The second voltage reference consumes 48pW from a supply voltage of 0.3V while having a reference voltage of 172mV and a TC of $26ppm/^{\circ}C$. The current reference consumes 246nA from a supply voltage of 0.75V with a reference current of 32.6nA and a TC of $262ppm/^{\circ}C$. The performances of the designed references have been verified through simulations.

• Korean Chemical Engineering Research
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• v.46 no.3
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• pp.486-491
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• 2008

This paper describes a model identification method that has been applied to a commercial 12-inch RTP (rapid thermal processing) equipment with an ultimate aim to develop a high-performance advanced controller. Seven thermocouples are attached on the wafer surface and twelve tungsten-halogen lamp groups are used to heat up the wafer. To obtain a MIMO balanced state space model, multiple SIMO (single-input multiple-output) identification with highorder ARX models have been conducted and the resulting models have been combined, transformed and reduced to a MIMO balanced state space model through a balanced truncation technique. The identification experiments were designed to minimize the wafer warpage and an output linearization block has been proposed for compensation of the nonlinearity from the radiation-dominant heat transfer. As a result from the identification at around 600, 700, and $800^{\circ}C$, respectively, it was found that $y=T(K)^2$ and the state dimension of 80-100 are most desirable. With this choice the root-mean-square value of the one-step-ahead temperature prediction error was found to be in the range of 0.125-0.135 K.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.