• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1005-1014
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• 1990

This paper proposes the control unit of a 32-bit high-performance RISC type microprocessor. This control unit controls the whole data path of target processor and on chip instruction/data caches in 4-stage pipelined scheme. For the improvement of speed, large parts of data path and control unit are designed by domino-CMOS and hard-wired circuit technology. First, in this paper, target processor's instruction set and data path are defined, and next, all signals needed to control the data path are analyzed. The decoder of control unit and clock generated logic block are implemented in DCAL(Dynamic CMOS Array Logic) with modified clock scheme for the purpose of speed up and supporting RISC processor's pipelined architecture efficiently.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.59-68
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• 1998

This paper propose a hardware architecure of multimediasysgem for integrated processing of the multimedia data such as audio and video, and describes on the design and implementation of multimedia integrated processing Unit. The unit comprises most commonly needed multimedia processing function for computer-based video conference: audio-visual datacapture, playback, compression, decompression as well as interleaving/disinterleaving of compressed audio-visual data. The proposed architecture minimizes the CPU overhead that might be caused by multimedia data processing and assures the fluent data flow among system components. Also, this unit is tested and analyzed under the computer-based video conference to confirm the multimedia unit of proposed architecture using communication protocol and application software through Ethernet and FDDI (Fiber Distributed Data Interface) networks.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.8
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• pp.7-14
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• 1992

This paper persents how the signal is expressed by an implied unit data and the implied unit data is regenerated into the original signal. This shows that the regenerated signal is equal or similar to the original signal depending on the number of chaos prediction. The algorithm quoted above is implemented from the signal composed of 30 data. This algorithm will be applied to the applied science of data communication: information storage, speech processing, CAD, character recognition, etc...

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.193-201
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• 1996

The space power system for communication satellite which employs the direct energy transfer (DET) method consists of solar array, battry, shunt regulator, charger/discharger and power control unit (PCU). In this paper, the development of the DET power system charger/discharger unit and a microprocessor based PCU is developed for simplicity and flexiblity in the modificatin of control algorithm. A 28V bus voltage, 400W power rting power simulator is built and tested to verify the operation of the simulator at each mode and the stability of mode transition is analyzed.

• Journal of Astronomy and Space Sciences
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• v.20 no.4
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• pp.359-364
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• 2003

In this paper, we present multi-sensor data fusion for telematics application. Successful telematics can be realized through the integration of navigation and spatial information. The well-determined acquisition of vehicle's position plays a vital role in application service. The development of GPS is used to provide the navigation data, but the performance is limited in areas where poor satellite visibility environment exists. Hence, multi-sensor fusion including IMU (Inertial Measurement Unit), GPS(Global Positioning System), and DMI (Distance Measurement Indicator) is required to provide the vehicle's position to service provider and driver behind the wheel. The multi-sensor fusion is implemented via algorithm based on Kalman filtering technique. Navigation accuracy can be enhanced using this filtering approach. For the verification of fusion approach, land vehicle test was performed and the results were discussed. Results showed that the horizontal position errors were suppressed around 1 meter level accuracy under simulated non-GPS availability environment. Under normal GPS environment, the horizontal position errors were under 40㎝ in curve trajectory and 27㎝ in linear trajectory, which are definitely depending on vehicular dynamics.

• Proceedings of the Korea Contents Association Conference
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• 2005.05a
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• pp.443-447
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• 2005

EMAST(Embedded Mobile Automatic System for Telematics) is implemented in SoC using the CAN and ARM Processor. For the general usage, EMAST must satisfy the two condition. First, Mobile internal interface is to be designed to support Differential Transceiver, Optical Transceiver and Wireless Transceiver Second, it should be supporting the interface between terminals using EMAST and telematics networks. In this paper, we propose EMAST structure and the efficient interface structure between EMAST and each mobile units.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.79-88
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• 1998

We developed a method for the solid angle estimation of acetabular coverage of the femoral head in 3D space. The superior half of the femoral head is modeled as part of a sphere. And the tangent lines connecting from a set of points of the acetabular outline to the center of the fitted sphere are obtained. The lines passthrough the unit sphere whose center is the same as that of the femoral head. The interesecting points form a boundary on the unit sphere. With the points on the unit sphere, we calculate the covered area of the femoral headand estimate the solid angle. Solid angle is defined asthe suface area within the boundary on the unit sphere. In this measurements, the solid angle of normal subjects is on an average 4.3(rad) and the corresponding acetabular coverage is 68%. Unlinke the conventional methods, this solid angle estimation shows real 3D acetabular coverage.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.404-410
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• 1991

In this paper,a network interface unit of token-passing bus network and its driving software are implemented based on Mini-MAP. This network interface unit performs the function of MAC layer which is responsible for transmission and reception of frames as well as the management of logical ring. The driving software performs the management of data buffer and the report of errors, if ocoured, to the higher layer. Motorola MC68824 of is used as a TBC(Token Bus Controller) and Intel80186 as a CPU for network interface unit. The operation of network interface unit is verified by self-test which checks the functioning of TBC and CPU. In addition each module of driving software is tested to check the functions regarding transmission and reception of frames.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.43-52
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• 1997

Processors using the superscalar rchitecture can achieve high performance by executing multipel instructions in a clock cycle. It is made possible by having multiple functional units and issuing multiple instructions to functional units simultaneously. But instructions can be dependent on one another and these dependencies prevent some instructions form being issued at the same cycle. In this paper, we designed an issue unit of a superscalar RISC microprocessor that can issue four instructions per cycle. The issue unit receives instructions form a prefetch unit, and issues them in order at a rate of as high as four instructions in one cycle for maximum utilization of functional units. By using an instruction buffer, the unit decouples instruction fetch and issue to improve instruction ussue rate. The issue unit is composed of an instruction buffer and an instruction decoder. The instruction buffer aligns and stores instructions from the prefetch unit, and sends the earliest four available isstructions to the instruction decoder. The instruction decoder decodes instructions, and issues them if they are free form data dependencies and necessary functional units and rgister file prots are available. The issue unit is described with behavioral level HDL (lhardware description language). The result of simulation using C programs shows that instruction issue rate is improved as the instruction buffer size increases, and 12-entry instruction buffer is found to be optimum considering performance and hardware cost of the instruction buffer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.910-920
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• 1990

This paper presents a method of constructing an Arithmetic Operation Unit Systems (A.O.U.S.) over Galois Field GF(2**m) for the purpose of the four arithmetical operation(addition, subtraction, multiplication and division between two elements in GF(2**mm). The proposed A.O.U.S. is constructed by following procedure. First of all, we obtained each four arithmetical operation algorithms for performing the four arithmetical operations using by mathematical properties over GF(2**m). Next, for the purpose of realizing the four arithmetical unit module (adder module, subtracter module, multiplier module and divider module), we constructed basic cells using the four arithmetical operation algorithms. Then, we realized the four Arithmetical Operation Unit Modules(A.O.U.M.) using basic cells and we constructd distributor modules for the purpose of merging A.O.U.M. with distributor modules. Finally, we constructed the A.O.U.S. over GF(2**m) by synthesizing A.O.U.M. with distributor modules. We prospect that we are able to construct an Arithmetic & Logical Operation Unit Systems (A.L.O.U.S.) if we will merge the proposed A.O.U.S. in this paper with Logical Operation Unit Systems (L.O.U.S.).