• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.7
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• pp.16-24
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• 1999

This paper deals with the dynamic vehicle arbitration algorithm for communication between vehicles and a roadside control init on multilane environment. The suggested algorithm varies its parameter values according to the current vehicle arrival rate to get the maximum performance. To get the optimum parameter values, arbitration methods that use random delay counter and persist mechanism were taken into account and the performance of these methods with respect to the vehicle arrival rate was analyzed by computer simulation. After applying the optimum parameter values to suggested algorithm, it is shown that more enhanced reliability was acquired This algorithm could be applied to various systems which include the communication between a transponder and a control unit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.1
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• pp.115-122
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• 1987

In this paper, we proposed an improved weakly-coupled power divider(TAP UNIT) for CATV and/or MATV systems, by which the degree of freedom in design and density of coupling interval are signifcantly increased compared with the intrinsic one even though the turn ratios are still of discrete values. On the other hand, the new design theory of a generalized n-way power divider with arbitrary dividing ratios, for CATV and/or MATV systems, which consists of ideal multiwinding transformers and resistors only was presented. Since the circuit elements is not frequency dependent, the proposed power divider is to be of considerably broad bandwidth. Furthermore, the experimental verification has been achieved, and, hence, the validity of the design theory proposed here is confirmed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.20-27
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• 1998

This paper describes color clustering method based on color difference in the uniform Munsell color space obtained from hue, saturation, and value. The proposed method operates in the uniform HSV color space which is approximated using ${L^*}{a^*}{b^*}$ coordinate system based on the RGB inputs. A clustering and color difference evaluation are proposed by thresholding NBS unit which is likely to Balinkin color difference equation. Region segmentation and isolation process are carried out ISO DATA algorithm which is a self iterative clustering technique. Through the clustering of 2 input images according to the threshold value, satisfactory results are obtained. So, in conclusion, it is possible to extract result of better region segmentation using human color perception of the objects.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.85-91
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• 1999

$H:LiNbO_3$ optical modulator with Cu/parylene electrode layer, which has a merits in the bandwidth, power consumption and fabrication conditions as compared with conventional Au/Cr/$SiO_2$, is proposed and fabricated. Analysis and design of optical modulator is performed by finite element calculation. Various unit processes for fabricating the proposed modulator, 1550nm $H:LiNbO_3$ optical waveguide, parylene buffer layer, and CPW Cu electrode, were developed, After dicing and end-face polishing of fabricated modulator chip, optical modulation responses as sawtooth electrical driving voltage has been measured at low frequencies. Properties of optical waveguide had not been changed before and after Cu/parylene electrode processes, which make confirm the reproducible fabrication of optical modulator.

• Journal of the Korea Society of Computer and Information
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• v.10 no.6 s.38
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• pp.355-364
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• 2005

Ubiquitous environment can be supported by various service on networked appliance, sensors and devices. In home network and telematics, open service gateway is widely used for ubiquitous environment and Present environment for service installation, deployment and execution. Service gateway is a middle layer which is located between service and various devices in ubiquitous environment and offers a unique opportunity for pervasive computing as a potential framework for achieving interoperability between various sensors, home appliances. and networked devices. In ubiquitous environments, these services must support the mobility among service gateway because users and devices has a mobility characteristic. However the OSGi framework supports only a remote installation of a bundle, which is a unit that installs and deploys services. This paper develops a system that can manage bundles for supporting this dynamic bundle's mobility between service gateway. This system we are proposing implements a bundle form which can perform in an OSGi framework as well as manage the mobile services. As a result, mobility in a ubiquitous computing environment will be supported more efficiently.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.9-16
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• 1999

We have investigated effects of local damage accumulation for ultra-low energy As and B ion implant using highly efficient molecular dynamics(MD) scheme. We simulated ion implantation by MD simulation using recoil ion approximation (RIA) method and local cell damage accumulation (LCDA) model proposed in the paper. Local damage accumulation probability function consisted of deposited energy in a unit cell, implant dose rate, target material, projectile atom, and recoil event number. The simulated results were good agreement with the experimental and other simulated results. The MDRANGE results without damage accumulation were different from SIMS data in the tail region. We also simulated 2 dimensional dopant and damage profiles using the local damage accumulation model and recoil ion approximation method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.147-155
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• 1989

In this paper, a real-time implementation of the TWS(track-while-scan) system using the high-speed DSP (digital signal processor) TMS320C25 is described. First, attempts have been made to investigate the FWL (finite word length) effect, which is caused by employing a fixed point arithmetic, of implementing the Kalman filter. The real-time TWS system consists of TWS arithmetic unit, scan converter, and system controller. In addition, the TWS system is in tegrated in the Multi-Bus. In experiment, it is observed that by employing the floating point arithmetic the computation time of 0.35sec is required for tracking 8 targets simultaneously, while 0.28sec is required for the fixed point arithmetic. Since the TWS system is designed to track up to 8 targets simultaneously, we conclude that the system is enough to process Kalman filter in a real-time.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.8-16
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• 1999

This paper describes a VLSI design of Reed-Solomon(RS) decoder using the modified Euclid algorithm, with the main theme focused on the $\textit{GF}(2^8)$. To get area-efficient design, a number of new architectures have been devised with maximal register and Euclidean ALU unit sharing. One ALU is shared to replace 18 ALUs which computes an error locator polynomial and an error evaluation polynomial. Also, 18 registers are shared to replace 24 registers which stores coefficients of those polynomials. The validity and efficiency of the proposed architecture have been verified by simulation and by FLEX$^TM$ FPGA implementation in hardware description language VHDL. The proposed Reed-Solomon decoder, which has the capability of decoding RS(208,192,17) and RS(182,172,11) for Digital Versatile Disc(DVD), has been designed by using O.6$\mu\textrm{m}$ CMOS TLM Compass$^TM$ technology library, which contains totally 17k gates with a core area of 2.299$\times$2.284 (5.25$\textrm{mm}^2$). The chip can run at 20MHz while the DVD requirement is 3.74MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.59-65
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• 1999

In this paper, we design a entorpy encoder of HDTV/DTV encoder blocks on the basis of MPEG-II. The designed entropy encoder outputs its bit stream at 9Mbps bit rate inserting zero-stepping block to protect the depletion of buffer in case that the generated bit stream is stored in buffer and uses not only PROM bit combinational circuit to solve the problem of critical path, and packer block, one of submerge, is designed to packing into 24 bit unit using barrel shifter, and it is constructed to blocks of header information encoder, input information delay, submerge, and buffer control. Designed circuits is verified by VHDL function simulation, as a result of performing P&R with Gate compiler that apply $0.8{\mu}m$ Gate Array specification, pin and gate number of total circuits has been tested to each 235 and about 120,000.