• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.79-84
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• 2007

In this paper, a fully-integrated low phase noise multi-band CMOS VCO using automatic level controller (ALC) and switched LC tank has been presented. The proposed VCO has been fabricated in a 0.13-um CMOS process. The switched LC tank has been designed with a pair of capacitors and two pairs of inductors switched using MOS switch. By using this structure, four band (2.986 ${\sim}$ 3.161, 3.488 ${\sim}$ 3.763, 4.736 ${\sim}$ 5.093, and 5.35 ${\sim}$ 5.887 GHz) operation is achieved in a single VCO. The VCO with 1.2 V power supply has phase noise of -118.105 dBc/Hz @ 1 MHz at 2.986 GHz and -113.777 dBc/Hz @ 1 MHz at 5.887 GHz, respectively. The reduced phase noise has been approximately -1 ${\sim}$ -3 dBc/Hz @ 1 MHz in the broadest tuning range, 2.986 ${\sim}$ 5.887 GHz. The VCO has consumed 4.2 ${\sim}$ 5.4 mW in the entire frequency band.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.189-194
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• 2017

The reversibility of a quantum logic circuit can be realized when two reversible conditions of information reversible and energy reversible circuits are satisfied. In this paper, we have modeled the computation cycle required to recover the information reversibility from the multivalued quantum logic to the original state. For modeling, we used a function embedding method that uses a unitary switch as an arithmetic exponentiation switch. In the quantum logic circuit, if the adjoint gate pair is symmetric, the unitary switch function shows the balance function characteristic, and it takes 1 cycle operation to recover the original information reversibility. Conversely, if it is an asymmetric structure, it takes two cycle operations by the constant function. In this paper, we show that the problem of 2-cycle restoration according to the asymmetric structure when the hybrid MCT gate is realized with the ternary M-S gate can be solved by equivalent conversion of the asymmetric gate to the gate of the symmetric structure.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.2
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• pp.20-27
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• 2001

3D image coding and transmission technologies are essential for transmitting 3D image information through the limited transmission channel, and very important in the area of information and telecommunication services using 3D image media. In this paper, we propose the 3D image coding and transmission methods welch use disparity information and MPEG-2's scalability. Left and Fight image sequences are coded in base layer and enhancement layer, respectively. The enhancement layer contains the disparity and prediction informations. In order to reduce searching time for disparity information, we propose a method in which the disparity information of previous image paid is used in the next image pair, and we adopt the bit rate control method proposed in MPEG-2 TM6. An experimental result showed that the proposed searching method considerably reduced the entire encoding time and reached the desired bit rates.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.46-55
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• 2014

PCB design technology for high-speed transmission line has been developed continuously. Adapting to the high capacity of the communication system, switch fabric interface used for backplane is being standardized to accommodate more than 10Gbps serial interface. In this paper, various computer simulations are performed to compare the performance of each transmission line per length according to PCB material, and also to analyze the effect from via stub length and crosstalk, for the purpose of applying 11.5Gbps serial interface as a switch fabric interface in tera-bit switching system. As a result of the simulation, important design issues, such as PCB material of each board supporting 8dB improvement in transmission loss using low loss PCB, maximum available stub length on transmission line via, whether or not to apply the backdrill process to the via, and the clearance of the differential pair between transmission lines, are determined. The most efficient system architecture which could be applied 11.5Gbps serial interface in all switch fabric interfaces is defined from the simulation results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.12
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• pp.9-16
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• 2005

A new online routing algerian is proposed in this paper, which use the interference-prediction to solve the network congestion originated from extension of Internet scope and increasing amount of traffic. The end-to-end QoS has to be guaranteed in order to satisfy service level agreements (SLAs) in the integrated networks of next generation. For this purpose, bandwidth is allocated dynamically and effectively, moreover the path selection algorithm is required while considering the network performance. The proposed algorithm predicts the level of how much the amount of current demand interferes the future potential traffic, and then minimizes it. The proposed algorithm considers the bandwidth on demand, link state, and the information about ingress-egress pairs to maximize the network performance and to prevent the waste of the limited resources. In addition, the interference-prediction supports the bandwidth guarantee in dynamic network to accept more requests. In the result, the proposed algorithm performs the effective admission control and QoS routing. In this paper, we analyze the required conditions of routing algorithms, the aspect of recent research, and the representative algorithms to propose the optimized path selection algorithm adequate to Internet franc engineering. Based on these results, we analyze the problems of existing algorithms and propose our algorithm. The simulation shows improved performance by comparing with other algorithms and analyzing them.