• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.3
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• pp.88-98
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• 2002

The multilayer perceptron (MLP) has several advantages against other pattern recognition methods, and is expected to be used as the learning and recognizing speakers of speaker verification system. But because of the low learning speed of the error backpropagation (EBP) algorithm that is used for the MLP learning, the MLP learning requires considerable time. Because the speaker verification system must provide verification services just after a speaker's enrollment, it is required to solve the problem. So, this paper tries to make short of time required to enroll speakers with the MLP based speaker verification system, using the method of improving the EBP learning speed and the method of reducing background speakers which adopts the cohort speakers method from the existing speaker verification.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.1
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• pp.51-58
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• 2022

Korea Augmentation Satellite System (KASS) is a Satellite Based Augmentation System (SBAS) system under development in South Korea and aims to provide air navigation services after 2023. In order to provide reliable service, detailed design for the operation of this system is required. This paper proposes a detailed operation-based designs based on mission, architecture, operation definition of the system. For the stable operation of the system, an operation organization was designed and operation activities were classified in consideration of the architecture and function of the system. Detailed operation procedures were designed according to this classification and operation procedures related to the command and configuration of subsystem were verified on the Integration, Verification and Qualification (IVQ) platform for integrated testing and verification. The proposed operation concepts and procedures will be continuously confirmed and verified during verification, qualification and service preparation, and will be updated event after official KASS service.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.4
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• pp.1360-1388
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• 2021

Shipbuilding and repairing enterprise has the characteristics of many hazards and accidents. Therefore, the safety management ability of shipbuilding and repairing MIS (management information system) must be effectively guaranteed. The verification on safety management is the necessary measure to ensure and improve the safety management ability of MIS. Safety verification can not only increase the safety of MIS, but also make early warning of potential risks in management to avoid the accidents. Based on the authoritative standards in the field of safety in shipbuilding and repairing enterprise, this paper applied modeling and verification method based on ontology to safety verification of MIS, extracted the concepts and associations from related safety standards to construct axiom set to support safety verification on MIS of shipbuilding and repairing enterprise. Then, this paper developed the corresponding safety ontology modeling and verification tool-SOMVT. By the application and comparison of two examples, this paper effectively verified the safety of MIS to prove the modeling method and the SOMVT can improve the safety of MIS in a much more effective and stable way to traditional manual analysis.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.1
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• pp.17-23
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• 2015

With the increase in the risk of GPS jamming, the development and application of anti-jamming GPS techniques have been actively performed. As the objective performance verification of developed techniques is important, equipment development for verification and discussion on anti-jamming performance test method and procedure have also been conducted. However, most tests are related to the specification of equipment and therefore detailed procedure of the performance verification of an anti-jamming system needs to be developed. In this study, requirements for anti-jamming performance verification were described, and test configurations and performance evaluation items depending on three kinds of test methods (lab test, basic outdoor test, and chamber test) were suggested for anti-jamming performance verification.

• Nuclear Engineering and Technology
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• v.41 no.1
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• pp.79-90
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• 2009

Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.409-416
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• 1996

This paper describes the simulation environment that verifies whether a new microporcessor described with HDL is compatible with an existing microprocessor. The compatibility verification is done by showing that the new microprocessor executes the OS(Operating System) program used in the existing microprocessor without any modification of its binary code. The proposed verification environment consists of a virtual system and a graphic user interface (GUI) module. Each module is independently designed based on serve-client model and three exists a communication part for information interchange between the two modules. This paper describes the method of constructing the verification environment and presents the compatibility verification environment of the x86 microprocessor as the simulation result.

• MALSORI
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• no.63
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• pp.153-170
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• 2007

It is well known that when there is an acoustic mismatch between the speech obtained during training and testing, the accuracy of speaker verification systems drastically deteriorates. This paper presents the use of MFCCs' histogram enhancement technique in order to improve the robustness of a speaker verification system. The technique transforms the features extracted from speech within an utterance such that their statistics conform to reference distributions. The reference distributions proposed in this paper are uniform distribution and beta distribution. The transformation modifies the contrast of MFCCs' histogram so that the performance of a speaker verification system is improved both in the clean training and testing environment and in the clean training and noisy testing environment.

• International Journal of Safety
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• v.3 no.1
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• pp.38-46
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• 2004

This paper introduces the software life-cycle V&V (verification and validation) tasks for the KNICS (Korea nuclear instrumentation and control system) project. The objectives of the V&V tasks are mainly to develop a programmable logic controller (PLC) for safety critical instrumentation and control (I&C) systems, and then to apply the PLC to developing the prototype of an engineered safety features-component control system (ESF-CCS) in nuclear power plants. As preparative works for the software V&V, various kinds of software plans and V&V task procedures have been developed according to the software life-cycle management. A number of software V&V tools have been adopted or developed to efficiently support the V&V tasks. The V&V techniques employed in this work include a checklist-based review and inspection, a requirement traceability analysis, formal verification, and life-cycle based software testing.

• Proceedings of the Korea Contents Association Conference
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• 2003.05a
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• pp.430-434
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• 2003

This article describes the survey of biometrics verification system and the analysis of evaluating performance methodology. For this, firstly, survey is performed biometrics verification methods and systems using bio-based features and behaviour-based features. Also, I want to analyze the trend and utilities of biometrics verification system by evaluating performance methodology.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.815-818
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• 1998

Hardware formal verification involves the use of analytical techniques to prove that the implementation of a system confroms to the specification. The specification could be a set of properties that the system must have or it could be an alternative representation of the system behavior. We can represent our behavioral specification to be written in VHDL coding. In this paper, we proposed a new hardware design verification method. For theis method, we assumed that a verification pattern already exists and try to make an algorithm to find a place where a design error occurred. This method uses an hierarchical approach by making control flow graph(CFG) hierarchically. From the simulation, this method was turned out to be very effective that all the assumed design errors could be detected.