• Journal of Information Processing Systems
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• 제15권6호
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• pp.1449-1461
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• 2019

Face sketch synthesis plays an important role in public security and digital entertainment. In this paper, we present a novel face sketch synthesis method via local similarity and nonlocal similarity regularization terms. The local similarity can overcome the technological bottlenecks of the patch representation scheme in traditional learning-based methods. It improves the quality of synthesized sketches by penalizing the dissimilar training patches (thus have very small weights or are discarded). In addition, taking the redundancy of image patches into account, a global nonlocal similarity regularization is employed to restrain the generation of the noise and maintain primitive facial features during the synthesized process. More robust synthesized results can be obtained. Extensive experiments on the public databases validate the generality, effectiveness, and robustness of the proposed algorithm.

• 한국멀티미디어학회논문지
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• 제11권12호
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• pp.1739-1748
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• 2008

When we conduct a data mining procedure on sample data sources, several rules are generated. But some rules are redundant or logically disjoint and therefore they can be removed. We suggest a new rule minimization algorithm inspired from logic synthesis to improve comprehensibility and eliminate redundant rules. The method can merge several relevant rules into one based on data mining and logic synthesis without high loss of accuracy. In case of two or more rules are candidates to be merged, we merge the rules with the attribute having the lowest information gain. To show the proposed method could be a reasonable solution, we applied the proposed approach to a problem domain constructing user preferred ontology in anti-spam systems.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.262-265
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국제학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.13-17
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• 1993

In this paper, a design method of controller which incorporates pole restriction into implicit self tuning algorithm is proposed. The idea behind pole restriction is that the closed loop poles of the system are restricted to a user-chosen circle in the region to meet maximum percentage overshoot and settling time specification. Most algorithm based on pole restriction are explicit schemes involving a parameter estimation and synthesis stage to obtain controller parameters. The object of this paper is to have an algorithm that has the idea of pole restriction and the simplicity of the implicit approach.

• 전자공학회논문지A
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• 제33A권10호
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• pp.81-89
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• 1996

In this paper, a very efficient CAD algorithm is proposedd where rhodes formulae combined with distributed lowpass prototype filter in order to design the corrugated waveguide harmonic rejection filters accurately. The proposed algorithm resolves effectively the problem of proximity effect without any optimiation or iterative design process by using the internally convexed corrugated structure. A 13-section tapered corrugated lowpass filter has been designed by the proposed algorithm and fabricated. The experimental results are in good agreement with the calculated results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.75-78
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• 2000

This paper presents a new algorithm for allocating the data path to achieve the minimum power consumption under the constraints of minimum hardware resources. In order to minimize the power consumption, the proposed algorithm tries to minimize the input transitions of functional units, unnecessary computations, and size of interconnects in a greedy manner during a]location. Experimental results using benchmarks indicate the proposed algorithm achieves 17.5% power reduction on average, when compared with the genesis-lp［1］high-level synthesis system.

• 전자공학회논문지C
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• 제34C권11호
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• Current Optics and Photonics
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• 제5권6호
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• pp.672-679
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• 2021

We propose a high-speed layer-based algorithm for synthesizing computer-generated holograms (CGHs), featuring sparsity-based image segmentation and computational parallelism. The sparsity-based image segmentation of layer-based three-dimensional scenes leads to considerable improvement in the efficiency of CGH computation. The efficiency enhancement of the proposed algorithm is ascribed to the field localization of the fast Fourier transform (FFT), and the consequent reduction of FFT computational complexity.

• 한국통신학회논문지
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• 제29권6C호
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• pp.874-882
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• 2004

MPEG 오디오 표준은 고품질 오디오를 제공하기 위해 인간 청각계의 지각현상을 이용한 오디오 압축 알고리듬이다. 다수의 표준안 중 MPEG-2 BC와 MPEG-2 AAC에 대한 공용 복호화 시스템은 아직 발표되어 있지 않다. 본 논문에서는 BC/AAC의 공용 시스템을 구축하여 복호화 과정에서 공통된 구조로 연산을 수행하고 면적감소, 비용절감 등을 목표로 한다. 본 논문에서는 공통된 연산구조를 가지기 위해서 recursive 구조를 이용하여 복호화 과정중 합성 필터링 과정을 공통된 구조로 연산을 수행할 수 있는 공용 합성 필터 구조를 제안한다. 제안한 구조는 연산시간의 개선을 위하여 고속 알고리듬을 적용하였으며 기존의 MPEG-2 AAC 함성 필터링에 대한 recursive 알고리듬을 2단 recursive 구조로 변경, 적용하였고 그 결과 같은 구조로 MPEG-2 BC의 서브밴드 합성필터링도 연산 가능함을 보였다.

• 한국정보통신학회논문지
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• 제8권8호
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• pp.1818-1827
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• 2004

본 논문에서는 압전평면판에 홈을 파 형성한 (equation omitted)형 선형배열음원과 최적화 알고리즘을 조합한 적응 지향성합성 시스템의 2차원 지향성합성 문제를 수치적으로 검토하였다. 임의로 설정한 목적 지향성을 실현하기 위하여 먼저, 선형배열 진동자의 최적 진동 변위량은 최적화 알고리즘인 DFP (Davidon-Fletcher-Powell) 법을 이용하여 계산하고, 다음에, 계산된 진동 변위량을 구동하기 위한 최적 전위의 계산은 유한요소법과 DFP법을 이용하여 행했다. 또한, 유한요소법을 이용하여 (equation omitted)형 압전 트랜스듀서의 2차원 진동해석을 행했다.