• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.835-842
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• 2004

In this paper, we have analyzed the MC-DS/CDMA system with input signal synchronized completely through adjustment of the gain in the PLL loop, by using the hybrid SC/MRC-(2/3) technique, which is said to one of the optimal diversity techniques under the multi-path fading environment, assuming that phase error is defined to the phase difference between the received signal from the multi-path and the reference signal in the PLL of the receiver. Also, assuming that the regarded radio channel model for the mobile communication is subject to the Nakagami-m fading channel, we have developed the expressions and performed the simulation under the consideration of various factor, in the MC/DS-CDMA system with the hybrid SC.MRC-(2/3) diversity method, such as the Nakagami fading index(m), $the\;number\;of\;paths\;(L_p),$ the number of hybrid SC.MRC-(2/3) $diversity\;branches\;(L,\;L_c),$ the number of users (K), the number of subcarriers (U), and the gain in the PLL loop. As a result of the simulation, it has been confirmed that the performance improvement of the system can be achieved by adjusting properly the PLL loop in order for the MC/DS-CDMA system with the hybrid SC/MRC-(2/3) diversity method to receive a fully synchronized signal. And the value of the gain in the PLL loop should exceed 7dB in order for the system to receive the signal with prefect synchronization, even though there might be a slight difference according to the values of the fading index and the spread processing gain of the subcarrier.

• International Journal of Aeronautical and Space Sciences
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• v.17 no.4
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• pp.501-517
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• 2016

Synchronized switch damping (SSD) is a structural vibration control technique in which a piezoelectric patch attached to or embedded into the structure is connected to or disconnected from the shunt circuit in order to dissipate the vibration energy of the host structure. The switching process is performed by a digital signal processor (DSP) which detects the displacement extrema and generates a command to operate the switch in synchronous with the structure motion. Recently, autonomous SSD techniques have emerged in which the work of DSP is taken up by a low pass filter, thus making the whole system autonomous or self-powered. The control performance of the previous autonomous SSD techniques heavily relied on the electrical quality factor of the shunt circuit which limited their damping performance. Thus in order to reduce the influence of the electrical quality factor on the damping performance, a new autonomous SSD technique is proposed in this paper in which a negative capacitor is used along with the inductor in the shunt circuit. Only a negative capacitor could also be used instead of inductor but it caused saturation of negative capacitor in the absence of an inductor due to high current generated during the switching process. The presence of inductor in the shunt circuit of negative capacitor limits the amount of current supplied by the negative capacitance, thus improving the damping performance. In order to judge the control performance of proposed autonomous SSDNCI, a comparison is made between the autonomous SSDI, autonomous SSDNC and autonomous SSDNCI techniques for the control of an aluminum cantilever beam subjected to both single mode and multimode excitation. A value of negative capacitance slightly greater than the piezoelectric patch capacitance gave the optimum damping results. Experiment results confirmed the effectiveness of the proposed autonomous SSDNCI technique as compared to the previous techniques. Some limitations and drawbacks of the proposed technique are also discussed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.7
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• pp.273-281
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• 2003

This paper proposes a new time synchronization scheme for the Automatic Identification System(AIS). The proposed scheme utilizes a Temperature Compensated Crystal Oscillator(TCXO) as a local reference clock, and consists of a Digitally Controlled Oscillator(DCO), a divider, a phase comparator, and register blocks. Primary time reference is IPPS from GPS receiver that is synchronized to Universal Time Coordinated(UTC). And if GPS is unavailable, other station's signal is utilized as secondary time reference. The phase comparator measures time difference between the 1PPS and the generated transmit clock. The measured time difference is compensated by controlling the DCO and the transmit clock is synchronized to the Universal Time Coordinated(UTC). The synchronized transmit clock(9600Hz) is divided into the transmitting time slot(37.5Hz). The proposed scheme is tested in an experimental AIS transponder set. The experimental result shows that the proposed module satisfies the timing specification of the AIS technical standard, ITU-R M.1371-1.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.809-812
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• 2013

This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform provided by Dynalith Systems consists of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. Design of Embedded system is executed in Flowrian2 of System Centroid Inc., in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1413-1421
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• 2014

This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform is consisted of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. design of Embedded system is executed in Flowrian II, in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

• Journal of the Korean Society of Radiology
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• v.4 no.3
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• pp.31-37
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• 2010

In this paper, a photovoltaic system is designed with PWM(Pulse Width Modulation) voltage source inverter. Proposed synchronous signal and control signal was processed by 56F8323 microprocessor for stable modulation. The PWM voltage source inverter using inverter consists of complex type of electric power converter to compensate for the defect, that is solar cell cannot be developed continuously by connecting with the source of electric power for ordinary use. It can cause the effect of saving electric power, from 10 to 20[%]. The PWM voltage source inverter operates in situation that its output voltage is in same phase with the utility voltage. In addition, I connected extra power to the system through operation the system voltage and inverter power in a synchronized way by extracting the system voltage so that the phase of the system and PWM voltage inverter can be synchronized. In the system of this research showed good results after being controlled in order to provide stable power to the load and the system through maintaining and low output power of harmonics.

• Journal of Positioning, Navigation, and Timing
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• v.5 no.4
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• pp.165-172
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• 2016

A Global Navigation Satellite System (GNSS), which is typically exemplified by the Global Positioning System (GPS), employs a open signal structure so it is vulnerable to spoofing electronic attack using a similar malicious signal with that used in the GPS. It is necessary to require a spoofing test evaluation environment to check the risk of spoofing attack and evaluate the performance of a newly developed anti-spoofing technique against spoofing attacks. The present paper proposed a simulation method of spoofing environment based on simulator that can be implementable in a test room and analyzed the spoofing simulation performance using commercial GPS receivers. The implemented spoofing simulation system ran synchronized two GPS simulator modules in a single scenario to generate both of spoofing and GPS signals simultaneously. Because the signals are generated in radio frequency, a commercial GPS receiver can be tested using this system. Experimental test shows the availability of this system, and anti-spoofing performance of a commercial GPS receiver has been analyzed.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2570-2575
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• 2003

Monitoring a power transmission line is significant for power electric companies. In this paper, we propose a new method for detecting an fault point of power transmission line by use of M-sequence correlation technique. In this method, detecting signal is used as one or plural M-sequences ( same characteristic polynomial, including normal and reverse mark, synchronized ). In receiving point, we make same sequence with the input one and take crosscorrelation function between M-sequence and the received signal. We can see transfer fanctions of plural paths between inputs and a output taps separated from different of delay times on the crosscorrelation function, and from these transfer fanctions, so we compare them when fault occurred with in usual.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1132-1135
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• 2002

In this paper, we propose a phase-locked loop (PLL) with dual loops in which advantages of both loops can be combined. Frequency-locked loop (FLL) which is composed of two frequency-to-voltage converters (FVC) and an amplifier makes the frequency synchronize very fast and output signal is synchronized in phase with the input reference signal by charge pump PLL. This structure can improve the trade-off between acquisition behavior and locked behavior.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.4
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• pp.336-345
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• 1996

The S.O(synchronous osillator) oscillates at its natural frequency without the externa applied signal. But if the external signal is applied, the S.O starts to track the external frequency which can be sinusoidal, pulsed or some other waveform. Thus, the output is synchronized with the wide range of tracking bandwidth to the external frequency. Specifically, the S.O also posses frequency division and multiplication capability. All of these indicate that the S.O can overcome the difficulties of syschronization in coherent digital communication systems. This papers proposed application of DS/SS communication with study on the synchronous properties of S.O.