• Title/Summary/Keyword: switches

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HMGB1 Switches Alkylating DNA Damage-Induced Apoptosis to Necrosis (HMGB1에 의한 alkylating DNA 손상에 의해 유도된 세포사멸의 세포괴사로의 전환)

  • Lee, Su-Yeon;Jeong, Eui-Kyong;Jeon, Hyun-Min;Ju, Min-Kyung;Kim, Cho-Hee;Park, Hye-Gyeong;Kang, Ho-Sung
    • Journal of Life Science
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    • v.21 no.7
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    • pp.953-960
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    • 2011
  • Necrosis is characterized by the cell membrane rupture and release of the cellular contents, including high-mobility group box 1 protein (HMGB1), into the extracellular microenvironment. HMGB1 acts as a transcriptional regulator in nuclei, but exerts a pro-inflammatory and tumor-promoting cytokine activity when released into the extracellular space. Its overexpression is associated with tumor progression and chemoresistance. Thus, HMGB1 acts as a clinically important molecule in tumor biology. In this study, we examined whether HMGB1 affects cell death induced by anti-cancer drugs. Here we show that HMGB1 prevented cisplatin (alkylating agent)-induced apoptosis and switched the cell fate to necrosis in MCF-7, MDA-MB231, and MDA-MB361 cells. Similar apoptosis-to-necrosis switch effects of HMGB1 were observed in cells treated with 4-HC, another alkylating agent. In contrast, HMGB1 did not exert any significant effects on docetaxel (DOC)-induced apoptosis in MCF-7 cells. We also show that cisplatin-induced apoptosis was switched to necrosis in MCF-7 multicellular tumor spheroids (MTS) that were cultured for 8 days and had necrotic cores, but DOC-induced apoptosis was prevented without the apoptosis-to-necrosis switch. Finally, the levels of RAGE, a receptor of HMGB1, were increased with extended culture of MTS. These findings demonstrate that HMGB1 switches alkylating agent-induced apoptosis to necrosis, suggesting that the strategy to prevent necrosis occurring as an undesirable action of alkylating agent-based chemotherapy should be delineated to improve the efficacy of chemotherapy for cancer.

NetFPGA-based Scheduler Implementation and its Performance Evaluation for QoS of Virtualized Network Resources on the Future Internet Testbed (미래인터넷 테스트베드 가상화 자원의 QoS를 위한 NetFPGA 기반 스케쥴러 구현 및 성능 평가)

  • Min, Seok-Hong;Jung, Whoi-Jin;Kim, Byung-Chul;Lee, Jae-Yong
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.8
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    • pp.42-50
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    • 2011
  • Recently, research activities on the future internet are being actively performed in foreign and domestic. In domestic, ETRI and 4 universities are focused on implementation of a testbed for research on the future internet named as 'FiRST(Future Internet Research for Sustainable Testbed)'. In the 'FiRST' project, 4 universities are performing a project in collaboration named as 'FiRST@PC' project that is for an implementation of the testbed using the programmable platform-based openflow switches. Currently, the research on the virtualization of the testbed is being performed that has a purpose for supporting an isolated network to individual researcher. In this paper, we implemented a traffic scheduler for providing QoS by using the programmable platform that performs a hardware-based packet processing and we are implemented a testbed using that traffic scheduler. We perform a performance evaluation of the traffic scheduler on the testbed. As a result, we show that the hardware-based NetFPGA scheduler can provide reliable and stable QoS to virtualized networks of the Future Internet Testbed.

A Calibration-Free 14b 70MS/s 0.13um CMOS Pipeline A/D Converter with High-Matching 3-D Symmetric Capacitors (높은 정확도의 3차원 대칭 커패시터를 가진 보정기법을 사용하지 않는 14비트 70MS/s 0.13um CMOS 파이프라인 A/D 변환기)

  • Moon, Kyoung-Jun;Lee, Kyung-Hoon;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.12 s.354
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    • pp.55-64
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    • 2006
  • This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

A Read-In Integrated Circuit for IR Scene Projectors Adopting a Sub-Frame Control Technique for Minimizing the Temperature Loss (온도 손실의 최소화를 위해 Sub-Frame 제어 기법을 적용한 적외선 영상 투사기용 신호입력회로)

  • Shin, Uisub;Cho, Min Ji;Kang, Woo Jin;Jo, Young Min;Lee, Hee Chul
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.8
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    • pp.113-118
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    • 2016
  • In this paper, a read-in integrated circuit (RIIC) for IR scene projectors (IRSPs) adopting a sub-frame control technique is proposed, which minimizes the reduction of the apparent temperature of the IR images projected from IRSPs operating at a frame rate of 30 Hz. The proposed sub-frame control technique significantly reduces the amount of scene data loss on capacitors, which is caused by leakage currents flowing through MOSFET switches during holding periods, by dividing a unit frame into 8 sub-frames and refreshing the same scene data for each sub-frame. A current-drive RIIC was designed for the higher apparent temperature of IR radiated from the emitter, and it receives the scene data as a form of analog voltages from an external DAC. A prototype chip with a $64{\times}32$ RIIC array was fabricated using Magnachip/SKhynix $0.35{\mu}m$ 2-poly 4-metal CMOS process, and the measured maximum output data current is $230.3{\mu}A$. This amount of current ensures the projection of IR images whose maximum apparent temperature is $366.2^{\circ}C$ in the mid-wavelength IR (MWIR) when applied to a prototype emitter having a resistance of $15k{\Omega}$.

A 0.16㎟ 12b 30MS/s 0.18um CMOS SAR ADC Based on Low-Power Composite Switching (저전력 복합 스위칭 기반의 0.16㎟ 12b 30MS/s 0.18um CMOS SAR ADC)

  • Shin, Hee-Wook;Jeong, Jong-Min;An, Tai-Ji;Park, Jun-Sang;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.7
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    • pp.27-38
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    • 2016
  • This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

An Auction based Hierarchical Link Allocation Algorithm for Throughput Improvement of Relay Station Systems (Relay Station 시스템의 Throughput 향상을 위한 Auction 기반 계층적 링크 할당 알고리듬)

  • Kang, Hae-Lynn;Yu, Hye-In;Kim, Nak-Myeong
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.6
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    • pp.11-18
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    • 2009
  • In this paper, a hierarchical link allocation algorithm between mobile stations (MSs) and the corresponding base station (BS) by an optimal utilization of relay stations (RSs) is proposed to improve throughput of RS systems. In the proposed hierarchical algorithm, each RS operates cognitive radio functions to sense the degree of satisfaction in the quality of services (QoSs) and then selects the candidate set of MSs to have links with the RS. Such information is reported to the BS, where an auction process is performed to get an optimal allocation of communication links between the MSs and the BS. To maximize system throughput, the proposed auction algorithm is conducted upon bidding prices of communication links, considering both the co-channel interference (CCI) information shared among adjacent cells and the QoS enhancement information for each MS collected from RSs. The BS then switches the communication links of the auction winner MSs through the corresponding RS. The computer simulation shows that the proposed algorithm enhances the user QoS more than the conventional algorithm, especially for RS systems with more users requiring higher QoS. The proposed algorithm has also been proved to have more robust performance than the conventional one when the traffic load is higher and the CCI becomes stronger.

High-Order Temporal Moving Average Filter Using Actively-Weighted Charge Sampling (능동-가중치 전하 샘플링을 이용한 고차 시간상 이동평균 필터)

  • Shin, Soo-Hwan;Cho, Yong-Ho;Jo, Sung-Hun;Yoo, Hyung-Joun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.2
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    • pp.47-55
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    • 2012
  • A discrete-time(DT) filter with high-order temporal moving average(TMA) using actively-weighted charge sampling is proposed in this paper. To obtain different weight of sampled charge, the variable transconductance OTA is used prior to charge sampler, and the ratio of charge can be effectively weighted by switching the control transistors in the OTA. As a result, high-order TMA operation can be possible by actively-weighted charge sampling. In addition, the transconductance generated by the OTA is relatively accurate and stable by using the size ratio of the control transistors. The high-order TMA filter has small size, increased voltage gain, and low parasitic effects due to the small amount of switches and sampling capacitors. It is implemented in the TSMC $0.18-{\mu}m$ CMOS process by TMA-$2^2$. The simulated voltage gain is about 16.7 dB, and P1dB and IIP3 are -32.5 dBm and -23.7 dBm, respectively. DC current consumption is about 9.7 mA.

Fault Tolerant Design of Universal Soft Controller for Advanced Power Reactor (신형원전(APR+)을 위한 범용소프트제어기의 내고장성 설계)

  • Ye, Song-Hae;Lyou, Joon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.9
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    • pp.279-286
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    • 2012
  • Recently, design of Universal Soft Controller(USC) has been applied to the advanced control room for nuclear power plant. USC is software-based manual control means to control safety components as well as non-safety components in the highly-integrated control room. Therefore, design feature of USC is essential for the implementation of a single workstation in the advanced control room. The traditional control room is replaced by computer-driven consolidated operator interfaces. Considering our design has further reduced the probability of USC spurious signals by requiring two distinct operator control actions to generate any control signal. The reality of USC does not increase the probability of reactor trip because the probability of spurious USC signal is negligible. Universal Soft Control represents a significant evolution in nuclear I&C/HSI System. USC integrates the indicators and controls from multiple divisions into a single integrated visual display unit(VDU) based HSI(Human System Interface). In order to prevent adverse influence on safety function performance from USC failure, ESFAS signals are applied to safety components or functions. In addition, safety manual switches have priority over USC's signals. Therefore, spurious USC signals can be momentarily blocked by selecting a soft control command from the safety VDU.

An Empirical Study on the Determinants of Customer Renewal Behavior for Tire Rental Servitization (제조기업의 서비스화 제공 형태와 고객 특성이 재계약에 미치는 요인에 관한 실증 연구: 타이어 렌탈 중심으로)

  • Hyun, Myungjin;Kim, Jieun
    • The Journal of the Korea Contents Association
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    • v.20 no.4
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    • pp.508-517
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    • 2020
  • Servitization presents an innovative model to create business value in the automotive industries. This study set out to introduce a servitization model based on the rental business of the tire industry and identify determinants to affect the renewal of contracts around the service types of servitization and the characteristics of customers. Independent variables include the service types, demographics and regions, and inflow channels in 163,742 contracts by case companies in the nation in 2016~2019 with the renewal of contracts as a dependent variable. Correlations between variables were analyzed through cross-tabulation and binary logistic regression analysis. The findings show that the contract renewal rate had positive(+) relations with customized service and negative(-) ones with vehicle maintenance service. There were differences in the contract renewal rate according to such customer characteristics as gender and region, but no clear correlations were found in the age group and vehicle type(domestic/foreign). Of the inflow channels, offline channels tended to have a higher renewal rate than online channels. At open malls, contract renewal increased by 8.4 times due to contract switches at offline channels. Based on these findings, the study discussed directions for practical strategies with regard to the development of new service, implementation of customer-centric servitization, and management of sales channels according to the servitization of manufacturers.

Research on High-Efficiency Power Conversion Structure for Railroad Auxiliary Power Supply(APS) System (철도차량 보조전원장치의 효율향상을 위한 새로운 전력변환회로 구조 연구)

  • Cho, In-Ho;Jung, Shin-Myung;Lee, Byoung-Hee
    • Journal of the Korean Society for Railway
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    • v.19 no.3
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    • pp.297-303
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    • 2016
  • This paper introduces auxiliary power supply systems (APS) for railroad applications and proposes a new power conversion structure for highly-efficient and lightweight APS systems. The proposed structure focuses on an improvement of the power density in APS. It eliminates unnecessary power conversion stages in the conventional APS structure by modulating the dc/dc converter circuit and the structure of the system. The dc/dc converter circuit used in the proposed structure is based on a multi-level half-bridge converter, a widely used topology in railroad APS applications; a flying capacitor is newly added to the conventional circuit. The added capacitor is used not only to enhance the soft switching condition of the switches, but also so that the new pantograph will have a side voltage source of a battery charger in the APS structure. Since the battery charger uses the pantograph side voltage source in the proposed structure, rather than using the output of the main dc/dc converter in the conventional structure, the size and efficiency of the main dc/dc converter are reduced and increased, respectively. To verify the effectiveness of the proposed structure, simulation results will be presented with metropolitan transit APS specifications.