• Proceedings of the IEEK Conference
• /
• 2000.06a
• /
• pp.123-126
• /
• 2000

In this paper, we are proposed to pushing window input buffer A.T.M Switch that is not use memory read and write of general window police. Pushing window switch is superior to general window switch in performance but is large to general window switch in cross point number. Max throughput and Cell occupying probability results are verified by analysis an simulation. The evaluation of performance is max throughput and cell loss probability and mean queue length.

• Proceedings of the KIEE Conference
• /
• 2000.07c
• /
• pp.2116-2118
• /
• 2000

In the technique of Q-switching, very fast electronically controlled optical shutters can be made by using the electro-optic effect in crystals or liquids. The driver for the Pockels cell must be a high-speed, high-voltage switch which also must deliver a sizeable current. Common switching techniques include the use of vacuum tubes, cold cathode tubes, thyratrons, SCRs, and avalanche transistors. Semiconductor devices such as SCRs, avalanche transistors, and MOSFETs have been successfully employed to drive Pockels cell Q-switch. In this study, a simple driver for the Pockels cell Q-switch was developed by using SCRs, pulse transformer and TTL ICs. The Pockels cell Q-switch which was operated by this driver was employed in pulsed Nd:YAG laser system to investigate the operating characteristics of this Q-switch. And we have investigated the output characteristics of this Q-switch as a function of the Q-switch delay time to Xe flashlamp current on.

• Journal of Internet Computing and Services
• /
• v.5 no.3
• /
• pp.45-56
• /
• 2004

In this paper, we propose ATM switch architecture including ALL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of m cells which consist of ALL type 1. ALL type 2, ALL type 3/4 and ALL type 5 cells. We propose two switch fabric methods; One supports the ALL type 2 cell processing per input port, the other global ALL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a merit for easy implementation and extensibility. In this paper, the AAL Type 2 switch module which adapts the former method is designed using VHDL language and implemented in FPGA chip. The designed AAL Type 2 switch module operates at 52MHz. The proposed ATM switch fabric is widely applicable to mobile communication, narrow band services over ATM network and wireless ATM as well as general ATM switching fabric.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.1
• /
• pp.162-172
• /
• 1997

In this paper, we investigated the performance of a binary feedback switch algorithm for the ABR(Available Bit Rate) service in ATM networks. A binary feedback switch is also called EFCI(Explicit Forward Congestion Indication) switch and can be classificed into input cell processing(IP) scheme according to processing methods for the EFCI bit in data-cell header. We proposed two implementation methods for the binary feedback switch according to EFCI-bit processing schemes, and analyzed the ACR(Allowed Cell Rate) of source and the queue length of switch for each scheme in steady state. In addition, we derived the upper and lower bounds for maximum and minimum queue lengths, respectively, and investigated the impact of ABR parameters on the queue length.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.05a
• /
• pp.390-393
• /
• 2003

In this paper, we study on an implementation of cell scheduler which arbitrates the ATM exchange efficiently and swiftly. The designed ATM cell scheduler of this paper is based on iSLIP scheduling algorithm. It is aimed at the high-speed implementation. The implemented cell scheduler approximately provides 100% throughput for cell scheduling. We present a basic structure for cell scheduler and describe by using the HDL and perform behavior level and timing simulation. The cell scheduler of this paper is designed to support 8-port switch fabric and can expand in 32-port switch fabric. The cell scheduler for supporting the 8-port switch fabric is designed in 2-stage pipelines for the grant and accept stages respectively.

• Journal of the Korea Society of Computer and Information
• /
• v.11 no.1 s.39
• /
• pp.157-165
• /
• 2006

This paper proposes a new output-buffered multicast ATM switch with tandem crosspoints switching fabric, named the MTCOS(Multicast Tandem Crosspoint Output-buffered Switch). The MTCOS consists of multiple simple crosspoint switch fabrics, named TCSF(Tandem Crosspoint Switch Fabric) , and concentrated output buffers for efficient multicasting. The TCSF resolves the cell delay deviation problem which the self-routing crossbar switches inherently have. Further, it offers multiple concurrent pathes from one input to multiple output ports. It also provides multi-channel switching by easy software configuration and has several desirable characteristics such as scalability, high Performance, and modularity. A shared traffic concentration and output queuing strategies of the MTCOS results in lower cell loss as well as lower cell delay time over a wide range of multicast traffic. Furthermore, it has lower hardware complexity than that of the SCOQ and Knockout multicast switch to achieve the same Knockout concentration rate as the conventional switches. It is shown that the proposed switch can be easily applied to design high performance for any multicast traffic by analytic analysis and computer simulation.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.130-133
• /
• 1998

A imput buffer typed ATM switch and an appropriate cell-scheduling algorithm are necessary for avoiding output blocking and internal blocking respectively. The algorithm determining a set of non-blocking data cells from the queues can greatly affect on the switch's throughput as well as the behavior of the queues. In this paper bit pattern optimization combined with the Token method in presented in order to improve the performance of ATM switch. The digital Hopfield neural cell scheduler is designed and used for the maximum numbers of cells in real-time

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.9
• /
• pp.1209-1218
• /
• 1995

In this paper, we develope an ATM switch simulator in order to evaluate the HAN/B-ISDN ATM switch currently being developed by ETRI. It models the basic cell switching functions of the target ATM switch with priority control and multicasting features and it also supports such various traffic models as random or bursty traffic, balanced or unbalanced traffic, multicast traffic models. Using this simulator, we can evaluate the performances of the ATM switch in terms of various performance indices, i.e. cell delay, cell loss probability, etc., and this simulator can be utilized in the system parameter tunings such as the common buffer size and address buffer size.

• Proceedings of the Korea Society for Simulation Conference
• /
• 1999.04a
• /
• pp.1-5
• /
• 1999

An ATM switch is the basic component of an ATM network, and its functioning is to switch incoming cells arriving at an input port to the output port associated with an appropriate virtual path. In case of an ATM switch with buffer sharing scheme, the performance analysis is very difficult due to the interactions between the address queues. In this paper, the influences of the degree of traffic burstiness and some traffic routing properties are investigated by using the simulation. Also, some cell access strategies including priority access and cell dropping are compared in terms of cell loss probability.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.6
• /
• pp.48-55
• /
• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.