• 한국시뮬레이션학회논문지
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• 제8권4호
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• pp.1-8
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• 1999

This paper proposes an ATM switch architecture called Output Queued Batcher-Banyan switch (OQBBS). It consists of a Sorting Module, Expanding Module, and Output Queueing Modules. The principles of channel grouping and output queueing are used to increase the maximum throughput of an ATM switch. One distinctive feature of the OQBBS is that multiple cells can be simultaneously delivered to their desired output. The switch architecture is shown to be modular and easily expandable. The performance of the OQBBS in terms of throughput, cell delays, and cell loss rate under uniform random traffic condition is evaluated by computer simulation. The throughput and the average cell delay are close to the ideal performance behavior of a fully connected output queued crossbar switch. It is also shown that the OQBBS meets the cell loss probability requirement of $10^{-6}$.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제12B권1호
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• pp.37-43
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• 2002

This paper proposes a new zero-current switching (ZCS) pulse-width modulation (PWM) switch cell that has no additional conduction loss of the main switch. In this cell, the main switch and the auxiliary switch turn on and turn off under zero current condition. The diodes commutate softly and the reverse recovery problems are alleviated. The conduction loss and the current stress of the main switch are minimized, since the resonating current for the soft switching does not flow through the main switch. Based on the proposed ZCS PWM switch cell, a new family of dc to dc PWM converters is derived. The new family of ZCS PWM converters is suitable for the high power applications employing IGBTs. Among the new family of dc to dc PWM converters, a boost converter was taken as an example and has been analyzed. Design guidelines with a design example are described and verified by experimental results from the 2.5㎾ prototype boost converter operating at 40KHz.

• Journal of Power Electronics
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• 제1권2호
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• pp.71-77
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• 2001

This paper proposes a new zero-current switching (ZCS) pulse-width modulation (PWM) switch cell that has no additional conduction loss of the main switch. In this cell, the main switch and the auxiliary switch turn on and turn off under zero current condition. The diodes commutate softly and the reverse recovery problems are alleviated. The conduction loss and the current stress of the main switch are minimized, since the resonating current stress of the main switch are minimized, since the resonating current for the soft switching does not flow through the main switch. Based on the proposed ZCS PWM switch cell, a new family of DC to DC PWM converters is derived. The new family of ZCS PWM converters is suitable for the high power applications employing IGBTs. Among the new family of DC to DB PWM converters, a boost converter was taken as an example and has been analyzed. Design guidelines with a design example are described and verified by experimental results from the 2.5 kW prototype converter operating at 40 kHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.950-952
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• 2001

This paper proposes a new zero-current transition (ZCT) pulse-width modulation (PWM) switch cell that overcomes the limitations of the conventional ZCT converters. The proposed ZCT cell provides zero-current-switching (ZCS) condition for the main switch and the auxiliary switch. The conduction loss and current stress of the main switch are minimized, since the circulating current for the soft switching does not flow through the main switch. The proposed ZCT PWM switch cell is suitable for the high power applications employing IGBTs. Design guidelines with a design example are described and verified by experimental results from the 1 kW prototype boost converter operating at 70kHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.289-440
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• 1998

This paper describes an interconnection network structure which transports information among processors through a high speed ATM switch. To efficiently use the high speed ATM switch for the message-based multiprocessor, we implemented the cell router that performs multiplexing and demultiplexing of cells from/to processors. In this system, we use the expanded internal cell format including 3bytes for switch routing information. This interconnection network has 3 stage routing strategies: ATM switch routing using switch routing information, cell router routing using a virtual path identifier (VPI) and cell reassembly routing using a virtual channel indentifier (VCI). The interconnection network consists of the NxN folded switch and N cell routers with the M processor interface. Therefore, the maximum number of NxM processors can be interconnected for message communication. This interconnection network using the ATM switch makes a significant improvement in terms of message passing latency and scalability. Additionally, we evaluated the transmission overhead in this interconnection network using ATM switch.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.273-276
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• 1998

This paper proposes a new Asynchronous Transfer Mode(ATM) switch architecture for the Broadband ISDN. The proposed switch has the architecture to prohibit the out-of-sequence in shared buffer switch system with being fixed buffer size in the out-buffered large scale ATM Switch System. then in this paper proposes cell resequence algorithm to decrease the out-of-sequence problem. also, we studied the out-of-sequence problem that was occurred by the cell transfer delay and the cell overflow due to the fixed buffer size when cell resequenced and we propose to implement optimal ACFIFO(Address Counter First In First Out) buffer size which has the minimized cell loss.

• 한국통신학회논문지
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• 제24권12A호
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• pp.1922-1931
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• 1999

멀티캐스트 트래픽의 특징은 한 노드에서 특정 다수노드로 셀을 전송하는 방법으로써 ATM 스위치의 중요한 기능으로 부각되고 있다. 그러나, 기존에 나와 있는 point-to-point 스위치로 멀티캐스트 기능을 수행할 경우 멀티캐스트 셀 뿐만 아니라 유니캐스트 셀도 복사망을 통과하게 되어 복사망에서 추가적인 부하가 발생된다. 이 추가적인 부하로 인하여 멀티캐스트 셀이 다른 셀과의 충돌로 셀이 손실되는 데드락 현상이 발생하여 전체 스위치 성능을 현저히 감소시킨다. 또한 입력 저장 스위치 (Input queued switch)구조는 전체 스위치의 성능을 저하시키는 HOL 블록킹(blocking)의 단점을 가지고 있다. 제안한 스위치 구조는 HOL 블록킹 및 데드락 현상을 줄이기 위하여 공유 메모리 스위치를 이용하였다. 스위치의 복잡도와 셀 처리 시간을 줄이고 처리율(throughput)의 향상을 위해 셀 형태에 따라 분리해서 경로 배정하는 방식과 제어부에서 최대 2N개의 셀들을 동시에 처리하는 스케줄링 기법을 이용하였다. 또한 특정 포트로 트래픽이 밀집되었을 때 발생하는 손실률을 줄이기 위하여 출력 메모리를 이용하였으며 메모리 효율성 향상을 위하여 입력 셀의 ?'?형태에 따라 셀들을 분리 저장하는 방식과출력 메모리에서 일정 시간이 지난 셀을 폐기하는 방식을 이용하였다. 제안한 스위치의 분석을 위하여 마코흐(Markov) 체인을 이용한 성능 해석을 실시하였고 버스트(burst) 트래픽 조건에서의 모의 실험을 통하여 제안한 방식과 기존의 방식간의 성능을 비교, 분석하였다.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.23-28
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• 2007

In this paper, we propose ATM switch structure including AAL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of AAL cells which consist of AAL type 1, AAL type 2, AAL type 3/4, and AAL type 5 cells. We propose two switch fabric methods; One supports the AAL type 2 cell processing per input port, the other global AAL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a strong point for easy implementation and extensibility. The proposed ATM switch fabric architecture is applicable to mobile communication, narrow band services over ATM network.

• Journal of Electrical Engineering and Technology
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• 제11권2호
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• pp.367-376
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• 2016

This paper presents a cell balancing method for a single switch flyback converter with a multi-winding transformer. The conventional method using a flyback converter with a multi-winding transformer is simple and easy to control, but the voltage of each secondary winding coil might be non-uniform because of the unequal effective turn-ratio. In particular, it is difficult to control the non-uniform effect using turn-ratios because secondary coil has a limited number of turns. The non-uniform secondary voltages disturb the cell balancing procedure and induce an unbalance in cell voltages. Individual cell control by adding a switch for each cell can reduce the undesirable effect. However, the circuit becomes bulky, resulting in additional loss. The proposed method here uses the conventional flyback converter with an adjustment made to the output filters of the cells, instead of the additional switch. The magnitude of voltage applied to a particular cell can be reduced or increased according to the adjusted filter and the selected switching frequency. An analysis of the conventional converter configuration and the filter design method reveals the possibility of adequate cell balancing control without any additional switch on the secondary side.

• 한국시뮬레이션학회논문지
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• 제8권1호
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• pp.51-61
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• 1999

A cell scheduling method of Queue for the ATM switch is proposed and simulated. In this paper, we present the cell scheduling method proper to the proposed queue and the improved queue with Queue Sharing(QS) structure for CBR, VBR, ABR traffic. The proposed QS structure minimizes the CLS(Cell Loss Ratio) of ABR traffic and decreases the CLR of bursty VBR traffic. Also we propose a cell scheduling method using VRR(Variable Round Robin) scheme proper to the high-speed(ATM) switch. The VRR scheme provides a fairness in terms of service chance for the queues in the ATM switch as well as QOS of their cell delay characteristic of CBR and VBR traffic, QOS of ABR CLR. The simulation results show the proposed method achieves excellent CLR and average cell delay performance for the various ATM traffic services in the Queue Sharing structure.