• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.274-276
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• 2008

This paper proposes an individual charge equalization converter using selective two current paths for series connected lithium-ion battery strings. In the proposed equalizer, a central equalization converter acting as a controllable current source is sequentially connected in parallel with individual batteries through an array of cell selection switches. A flyback converter with a modified rectifier realizes a controllable current source. A central equalization converter is shared by every battery cells through the cell selection switch, instead of a dedicated charge equalizer for each cell. With this configuration, although the proposed equalizer has one dc-dc converter, individual charge equalization can be effectively achieved for the each cell in the strings. Furthermore, since the proposed equalizer would not allocate the separated dc-dc converter to each cell, such that the implementation of great size reduction and low cost can be allowed. In this paper, an optimal power rating design guide is also employed to obtain a minimal balancing size while satisfying equalization requirements. A prototype for eight lithium-ion battery cells is optimally designed and implemented. Experimental results verify that the proposed equalization method has good cell balancing performance showing small size, and low cost.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2012년도 춘계학술발표대회 논문집
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• pp.427-432
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• 2012

This paper proposes efficient operation method of PV system consisted of multi-central which is suitable for large scale system. The multi-central system used switch at a DC-link and applied proposed algorithm can improve the efficiency and the reliability on the existing system. This algorithm, with advantage of Multi-Central system can minimize the effect of different characteristic of each PV array due to a shadow or damaged PV cell. Each system is analysed and maximum power point tracking control, DC-link voltage control and output current control is used commonly. The validity is verified after comparing of the existing system and proposed system by simulation.

• 전자공학회논문지A
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• 제33A권11호
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• pp.140-151
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• 1996

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

• Journal of Power Electronics
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• 제8권4호
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• pp.363-370
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• 2008

In this paper, three kinds of PWM strategies for a three-phase current-fed dc/dc converter are proposed and compared in terms of losses and voltage transfer ratio. Each PWM strategy is described graphically and their switching losses are analyzed. With the proposed PWM C strategy, one turn-off switching of each bridge switch is eliminated to reduce switching losses under the same switching frequency. In addition, RMS current through the bridge switches is lowered by using parallel connection between two bridge switches and thus, conduction losses of the switches are reduced. Further, copper losses of the transformer are decreased due to the reduced RMS current of each transformer's winding. Therefore, total losses are minimized and the efficiency of the converter is improved by using the proposed PWM C strategy. Digital signal processor (DSP: TI320LF2407) and a field-programmable gate array (FPGA: EPM7128) board are used to generate PWM patterns for three-phase bridge and clamp MOSFETs. A 500W prototype converter is built and its experimental results verify the validity of the proposed PWM strategies.

• 한국항공우주학회지
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• 제34권4호
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• pp.89-101
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• 2006

본 논문에서는 HAUSAT-2 전력계의 설계와 각 모드별로 에너지 평형 해석을 통한 전력계 설계의 타당성을 검증하였다. 태양전지판은 GaAs 셀을 사용하였고 디지털 방식의 최대 전력 추적기를 채택하였다. 배터리 팩은 4개의 Li-Ion 셀로 구성하였고 최대 전력 추적기와 배터리 충전 조절기로 배터리 충전 기능을 구현하였다. 전력 제어기는 DC-DC 변환기로 요구되는 전압을 출력하고 상용 IC 및 MOSFET으로 이루어진 전력 분배기가 서브시스템 및 탑재체에 전력을 분배시킨다. 전력생성 분석은 다양한 승교점 지방시(LTAN)를 가지는 궤도를 고려하여 수행하였으며, 이 중 HAUSAT-2의 임무 수행에 적합한 궤도를 선정하여 모드별 전력 사항을 반영하여 에너지 평형 해석(EBA)을 진행하였다.

• 센서학회지
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• 제16권6호
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• pp.475-483
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• 2007

This paper proposes a readout integrated circuit (ROIC) for $32{\times}32$ infrared focal plane array (IRFPA) detector, which consist of reference resistor, detector resistor, reset switch, integrated capacitor and operational amplifier. Proposed ROIC is designed using $0.35{\;}{\mu}m$ 2P-4M (double poly four metal) n-well CMOS process parameters. Low noise folded cascode operational amplifier which is a key element in the ROIC showed 12.8 MHz unity-gain bandwidth and open-gain 89 dB, phase margin $67^{\circ}$, SNR 82 dB. From proposed circuit, we gained output voltage variation ${\Delta}17{\};mV/^{\circ}C$ when the detector resistor varied according to the temperature.

• ETRI Journal
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• 제41권6호
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• pp.715-730
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• 2019

We propose a switched beam-forming antenna that satisfies not only ultra-wideband characteristics but also beam-forming in the WLAN frequency band using an ultra-wideband antenna and passive parasitic elements applying a broadband optimal reactance load algorithm. We design a power and phase estimation function and an error correction function by re-analyzing and normalizing all the components of the parasitic array using control system engineering. The proposed antenna is compared with an antenna with a pin diode and reactance load value, respectively. The pin diode is located between the passive parasitic elements and ground plane. An antenna beam can be formed in eight directions according to the pin diode ON (reflector)/OFF (director) state. The antenna with a reactance load value achieves a better VSWR and gain than the antenna with a pin diode. We confirm that a beam is formed in eight directions owing to the RF switch operation, and the measured peak gain is 7 dBi at 2.45 GHz and 10 dBi at 5.8 GHz.

• 한국진공학회지
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• 제17권4호
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• pp.253-261
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• 2008

Programmable metalization cell (PMC) memory 소자로도 명명되는 고체 전해질 메모리 소자는 비휘발성, 고속 및 높은 ON/OFF 저항비 등을 갖고 있기 때문에, 차세대 비휘발성 메모리로서 각광받고 있는 소자 중의 하나이다. 본 논문에서는 고체 전해질 메모리 소자의 동작 원리를 먼저 소개하고자 한다. 또한, 메모리향 소자 개발을 진행 중인 미국 코지키 교수 그룹, 비메모리향 소자 개발을 진행 중인 일본 NEC 그룹 등의 해외 연구진과, Te 계열의 칼코게나이드 합금을 채택하여 소자를 제작한 한국전자통신연구원 및 충남대학교 등의 국내 연구진의 연구 성과를 소개하고자 한다.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2004년도 춘계학술대회 논문집
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• pp.442-446
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• 2004

KOMPSAT series use software-controlled unregulated bus system in which the main bus is directly connected to a battery and the duty-ratio for PWM switch is controlled by the on-board satellite software. This paper proposes a new power-stage circuit that can be available for modularization of the power regulator which is used at the software-controlled unregulated bus system satellite. And we analyze the proposed power-stage operation according to its operating modes and verify it by performing software simulation and hardware experiment using prototype. We constructs a parallel-module converter which is composed of proposed power-stages and perform experiment to verify modular characteristics of the proposed power-stage. Finally, we verify the usefulness of the proposed power-stage by comparing above results with those of a parallel-module converter made of conventional power-stages.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.55-55
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• 2010

We use ab initio density functional theory to determine the effect of bundling on the equilibrium structure, electronic and magnetic properties of $Mo_6S_{9-x}I_x$nanowires with x = 0, 3, 4.5, 6. Each unit cell of these systems contains two $Mo_6S_{6-x}I_x$ clusters connected by S3 linkages to form an ordered linear array. Due to the bi-stability of the sulfur linkages, the total energy of the nanowires exhibits typically many minima as a function of the wire length. We find that nanowires can switch over from metallic to semiconducting by applying axial stress. Structural order is expected in bundles with x=0 and x=6, since there is no disorder in the decoration of the Mo clusters. In bundles with other stoichiometries, we expect structural disorder to occur. We find the optimum inter-wire distance to depend sensitively on the orientation of the wires, but only weakly on x. It is also found that the electronic properties of nanowires are affected strongly due to bundling of nanowires exhibiting very unusual Fermi surfaces. Furthermore, ferromagnetic behaviors are observed in selected stable and many more unstable atomic arrangements in nanowire bundles.