• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.2 s.314
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• pp.74-81
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• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of H.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation and in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA(Field Programmable Gate Array) implementation results for the proposed structure show 39% and 32% gate count reduction in comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.825-827
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• 2010

본 논문에서는 여러 스테레오 매칭 알고리즘에서 차이값 생성에 사용되는 SAD(Sum of Absolute Differences)의 윈도우 기반 하에서 효율적인 수행에 관해 제시한다. 본 $8{\times}8$ 윈도우 기반의 SAD는 데이터 입력 상태와 데이터 쉬프트 상태로 나뉜다. 데이터 쉬프트 상태에서 디스패리티가 $8{\times}8$ 개의 데이터가 한 클럭에 한번에 생성이 되며 쉬프트 동작으로 데이터 코스트의 연속적인 생성이 가능하다. 본 논문에서는 $8{\times}8$ 윈도우 기반의 SAD를 설계하고 검증한다.

• ETRI Journal
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• v.34 no.5
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• pp.753-758
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• 2012

As the next-generation video coding standard, High Efficiency Video Coding (HEVC) has adopted advanced coding tools despite the increase in computational complexity. In this paper, we propose a selective bi-prediction method to reduce the encoding complexity of HEVC. The proposed method evaluates the statistical property of the sum of absolute differences in the motion estimation process and determines whether bi-prediction is performed. A performance comparison of the complexity reduction is provided to show the effectiveness of the proposed method compared to the HEVC test model version 4.0. On average, 50% of the bi-prediction time can be reduced by the proposed method, while maintaining a negligible bit increment and a minimal loss of image quality.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.263-264
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• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of 0.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation or in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA implementation results for the proposed structure show 39% and 32% gate count reduction comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

• Journal of KIISE:Software and Applications
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• v.33 no.4
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• pp.411-417
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• 2006

Motion Estimation (ME) is an important part of video coding process and it takes the largest amount of computation in video compression. Half-pixel and quarter-pixel motion estimation can improve the video compression rate at the cost of higher computational complexity In this paper, we suggest a new efficient low-complexity algorithm for half-pixel and quarter pixel motion estimation. It is based on the experimental results that the sum of absolute differences(SAD) shows parabolic shape and thus can be approximated by using interpolation techniques. The sub-pixel motion vector is searched from the minimum SAD integer-pixel motion vector. The sub-pixel search direction is determined toward the neighboring pixel with the lowest SAD among 8 neighbors. Experimental results show that more than 20% reduction in computation time can be achieved without affecting the quality of video.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.322-325
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• 2011

스테레오 비전 시스템에서 전통적인 매칭 알고리즘으로 SAD(Sum of Absolute Differences), SSD(Sum of Squared Differences), NCC(Normalized Cross Correlation) 등 다양한 알고리즘이 존재한다. 그러나 하드웨어로 실시간 처리를 위한 시스템을 구현하기 위해서는 리소스가 한정 되어있다는 제약 때문에 많은 연구에서 SAD 혹은 RT(Rank Transform), CT(Census Transform)를 많이 사용하게 된다. FPGA 내부에는 BRAM(Block RAM)과 MAC(multiply-accumulator)인 DSP슬라이스가 이미 존재한다. 본 논문에서는 BRAM과 DSP로직을 활용해서 전통적인 매칭 알고리즘 중에서 연산기 사용이 가장 많은 NCC를 FPGA로 실시간 처리 가능한 하드웨어 구조를 제안한다.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.22 no.2
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• pp.91-100
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• 2018

In this paper, we propose a new method for template matching, patch ratio, to inpaint unknown pixels. Before this paper, many inpainting methods used sum of squared differences(SSD) or sum of absolute differences(SAD) to calculate distance between patches and it was very useful for closest patches for the template that we want to fill in. However, those methods don't consider about geometric similarity and that causes unnatural inpainting results for human visuality. Patch ratio can cover the geometric problem and moreover computational cost is less than using SSD or SAD. It is guaranteed about finding the most similar patches by Cauchy-Schwarz inequality. For ignoring unnecessary process, we compare only selected candidates by priority calculations. Exeperimental results show that the proposed algorithm is more efficent than Criminisi's one.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.730-737
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• 2013

In this paper, Constrained One-Bit Transform (C1BT) based motion estimation using extension of matching error criterion is proposed. C1BT based motion estimation algorithm exploiting Number of Non-Matching Points (NNMP) instead of Sum of Absolute Differences (SAD) that used in the Full Search Algorithm (FSA) facilitates hardware implementation and significantly reduces computational complexity. However, the accuracy of motion estimation is decreased. To improve inaccurate motion estimation, this algorithm based motion estimation extending matching error criterion of C1BT is proposed in this paper. Experimental results show that proposed algorithm has better performance compared with the conventional algorithm in terms of Peak-Signal-to-Noise-Ratio (PSNR).

• Convergence Security Journal
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• v.13 no.3
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• pp.9-15
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• 2013

Calculating of matching cost is an important for efficient stereo matching. To investigate the performance of matching process, the concepts of the existing methods are introduced. Also we analyze the performance and merits of them. The simplest matching costs assume constant intensities at matching image locations. We consider matching cost functions which can be distinguished between pixel-based and window-based approaches. The Pixel-based approach includes absolute differences (AD) and sampling-intensitive absolute differences (BT). The window-based approach includes the sum of the absolute differences, the sum of squared differences, the normalized cross-correlation, zero-mean normalized cross-correlation, census transform, and the absolute differences census transform (AD-Census). We evaluate matching cost functions in terms of accuracy and time complexity. In terms of the accuracy, AD-Census method shows the lowest matching error ratio (the best solution). The ZNCC method shows the lowest matching error ratio in non-occlusion and all evaluation part. But it performs high matching error ratio at the discontinuities evaluation part due to blurring effect in the boundary. The pixel-based AD method shows a low complexity in terms of time complexity.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.104-107
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• 2010

본 논문은 H.264/AVC 디코더의 하드웨어 구현 시 가장 많은 시간을 소비하는 부분이 움직임 추정기를 하드웨어로 구현하였다. 움직임 추정을 함에 있어서 외부메모리 Access 량을 줄이고, SAD연산을 수행할 때 Clock의 손실 없이 계산을 하는 움직임 예측기를 제안한다. 제안한 구조는 재탐색 구간에서 이전 탐색 범위와 공통부분을 이루는 부분을 레지스터에 따로 저장해 두었다가, 재탐색시에 이전 Data를 사용하는 방법을 이용하였다. 움직임 추정을 수행할 때의 SAD (Sum of absolute differences)연산 부분과 Adder-tree를 묶은 PU Array와 SAD 누적기, 선택기를 Pipelining을 통하여 Clock의 손실 없이 연속적으로 계산하는 움직임 예측기를 설계하였다. 구현한 하드웨어는 최대 446.43MHz의 주파수에서 동작할 수 있었고, 탐색영역 64${\times}$64, 참조 프레임 3, 그리고 영상크기 1920${\times}$1080 기준으로 구현한 결과 50 프레임을 처리할 수 있는 성능을 보였다.