• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.226-233
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• 2014

This paper presents an external light evasion method that rectifies the problem of misrecognition due to external lighting. The fundamental concept underlying the proposed method involves recognition of the differences between two images and elimination of the desynchronized external light by synchronizing the image sensor and inner light source of the optical touch screen. A range of artificial indoor light sources and natural sunlight are assessed. The proposed system synchronizes with a Vertical Synchronization (VSYNC) signal and the light source drive signal of the image sensor. Therefore, it can display synchronized light of the acquired image through the image sensor and remove external light that is not from the light source. A subtraction operation is used to find the differences and the absolute value of the result is utilized; hence, the order is irrelevant. The resulting image, which displays only a touched blob on the touchscreen, was created after image processing for coordination recognition and was then supplied to a coordination extraction algorithm.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1345-1359
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• 1996

This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.910-920
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• 1990

This paper presents a method of constructing an Arithmetic Operation Unit Systems (A.O.U.S.) over Galois Field GF(2**m) for the purpose of the four arithmetical operation(addition, subtraction, multiplication and division between two elements in GF(2**mm). The proposed A.O.U.S. is constructed by following procedure. First of all, we obtained each four arithmetical operation algorithms for performing the four arithmetical operations using by mathematical properties over GF(2**m). Next, for the purpose of realizing the four arithmetical unit module (adder module, subtracter module, multiplier module and divider module), we constructed basic cells using the four arithmetical operation algorithms. Then, we realized the four Arithmetical Operation Unit Modules(A.O.U.M.) using basic cells and we constructd distributor modules for the purpose of merging A.O.U.M. with distributor modules. Finally, we constructed the A.O.U.S. over GF(2**m) by synthesizing A.O.U.M. with distributor modules. We prospect that we are able to construct an Arithmetic & Logical Operation Unit Systems (A.L.O.U.S.) if we will merge the proposed A.O.U.S. in this paper with Logical Operation Unit Systems (L.O.U.S.).

• East Asian mathematical journal
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• v.30 no.4
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• pp.509-526
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• 2014

The mathematics has moved toward the independence from unit. However, is this tendency also kept up in teaching and learning mathematics? This study starts from this question. We have illuminated this question in respects of a character of unit operation, an essential probability of unit operation and a didactical application of unit. As results, addition and subtraction are operations on identical objects and the result of operation does not also get out of operation's object. On the other hand, multiplication and division are operations on both identical objects and different objects. And the result of operation can generate new unit. We proposed a hypothesis which multiplication and division are transcendental operations from this analysis. The unit operation is not possible essentially. It seems only like unit operation is possible superficially by operational definition on unit. We could discuss on a didactical application of unit from above analysis. And we could deduct implications that the direction of developing mathematic does not necessarily match with the direction of teaching and learning mathematics.

• Journal of Elementary Mathematics Education in Korea
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• v.14 no.2
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• pp.241-262
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• 2010

This study was carried out to identify the cognitive obstacles while using addition and subtraction with fractions, and to analyze the sources of cognitive obstacles. For this purpose, the following research questions were established : 1. What errors do elementary students make while performing the operations with fractions, and what cognitive obstacles do they have? 2. What sources cause the cognitive obstacles to occur? The results obtained in this study were as follows : First, the student's cognitive obstacles were classified as those operating with same denominators, different denominators, and both. Some common cognitive obstacles that occurred when operating with same denominators and with different denominators were: the students would use division instead of addition and subtraction to solve their problems, when adding fractions, the students would make a natural number as their answer, the students incorporated different solving methods when working with improper fractions, as well as, making errors when reducing fractions. Cognitive obstacles in operating with same denominators were: adding the natural number to the numerator, subtracting the small number from the big number without carrying over, and making errors when doing so. Cognitive obstacles while operating with different denominators were their understanding of how to work with the denominators and numerators, and they made errors when reducing fractions to common denominators. Second, the factors that affected these cognitive obstacles were classified as epistemological factors, psychological factors, and didactical factors. The epistemological factors that affected the cognitive obstacles when using addition and subtraction with fractions were focused on hasty generalizations, intuition, linguistic representation, portions. The psychological factors that affected the cognitive obstacles were focused on instrumental understanding, notion image, obsession with operation of natural numbers, and constraint satisfaction.

• Journal of Korea Multimedia Society
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• v.12 no.1
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• pp.107-121
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• 2009

First reason for generation of standby power is because starting voltage must pass through from the source of electricity to IC. The second reason is due to current when IC is in operation. Purpose of this abstract is on structures of simple modules that automatically switch on or off through analysis of state on standby power and analysis of cutoff point patterns as well as application of algorithms. To achieve this, this paper is based on analysis of electric signals and modeling. Also, on/off cutoff criteria has been established for reduction of standby power. To find on/off cutoff point, that is executed algorithm of similar group and leading pattern group generation in the standby power state. Therefore, the algorithm was defined as an important parameter of the subtraction value of calculated between $1^{st}$ SCS, $2^{nd}$ SCS, and the median value of sampling coefficient per second from a wall outlet.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.348-355
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• 2011

In this paper, we propose an automatic prostate segmentation method from dynamic magnetic resonance (MR) images. Our method detects contrast-enhanced images among the dynamic MR images using an average intensity analysis. Then, the candidate regions of prostate are detected by the B-spline non-rigid registration and subtraction between the pre-contrast and contrast-enhanced MR images. Finally, the prostate is segmented by performing a dilation operation outward, and sequential shape propagation inward. Our method was validated by ten data sets and the results were compared with the manually segmented results. The average volumetric overlap error was 6.8%, and average absolute volumetric measurement error was 2.5%. Our method could be used for the computer-aided prostate diagnosis, which requires an accurate prostate segmentation.

• Journal of Mechanical Science and Technology
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• v.19 no.2
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• pp.549-557
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• 2005

The requirements of multi-resolution models of feature-based solids, which represent an object at many levels of feature detail, are increasing for engineering purposes, such as analysis, network-based collaborative design, virtual prototyping and manufacturing. To provide multi-resolution models for various applications, it is essential to generate adequate solid models at varying levels of detail (LOD) after feature rearrangement, based on the LOD criteria. However, the non-commutative property of the union and subtraction Boolean operations is a severe obstacle to arbitrary feature rearrangement. To solve this problem we propose history-based Boolean operations that satisfy the commutative law between union and subtraction operations by considering the history of the Boolean operations. Because these operations guarantee the same resulting shape as the original and reasonable shapes at the intermediate LODs for an arbitrary rearrangement of its features, various LOD criteria can be applied for multi-resolution modeling in different applications.