• ETRI Journal
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• v.30 no.1
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• pp.170-172
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• 2008

A substitution box (S-box) plays a central role in cryptographic algorithms. In this paper, an efficient method for designing S-boxes based on chaotic maps is proposed. The proposed method is based on the mixing property of piecewise linear chaotic maps. The S-box so constructed has very low differential and linear approximation probabilities. The proposed S-box is more secure against differential and linear cryptanalysis compared to recently proposed chaotic S-boxes.

• ETRI Journal
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• v.42 no.4
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• pp.619-632
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• 2020

Highly dispersive S-boxes are desirable in cryptosystems as nonlinear confusion sublayers for resisting modern attacks. For a near optimal cryptosystem resistant to modern cryptanalysis, a highly nonlinear and low differential probability (DP) value is required. We propose a method based on a piecewise linear chaotic map (PWLCM) with optimization conditions. Thus, the linear propagation of information in a cryptosystem appearing as a high DP during differential cryptanalysis of an S-box is minimized. While mapping from the chaotic trajectory to integer domain, a randomness test is performed that justifies the nonlinear behavior of the highly dispersive and nonlinear chaotic S-box. The proposed scheme is vetted using well-established cryptographic performance criteria. The proposed S-box meets the cryptographic performance criteria and further minimizes the differential propagation justified by the low DP value. The suitability of the proposed S-box is also tested using an image encryption algorithm. Results show that the proposed S-box as a confusion component entails a high level of security and improves resistance against all known attacks.

• Computers and Concrete
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• v.34 no.1
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• pp.79-91
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• 2024

In symmetric cryptography, a cryptographically secure Substitution-Box (S-Box) is a key component of a block cipher. S-Box adds a confusion layer in block ciphers that provide resistance against well-known attacks. The generation of a cryptographically secure S-Box depends upon its generation mechanism. In this paper, we propose a novel framework for the construction of cryptographically secure S-Boxes. This framework uses a combination of linear fractional transformation and permutation functions. S-Boxes security is analyzed against well-known security criteria that include nonlinearity, bijectiveness, strict avalanche and bits independence criteria, linear and differential approximation probability. The S-Boxes can be used in the encryption of any grayscale digital images. The encrypted images are analyzed against well-known image analysis criteria that include pixel changing rates, correlation, entropy, and average change of intensity. The analysis of the encrypted image shows that our image encryption scheme is secure.

• ETRI Journal
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• v.37 no.5
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• pp.1012-1022
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• 2015

Conventional cryptographic algorithms are not sufficient to protect secret keys and data in white-box environments, where an attacker has full visibility and control over an executing software code. For this reason, cryptographic algorithms have been redesigned to be resistant to white-box attacks. The first white-box AES (WB-AES) implementation was thought to provide reliable security in that all brute force attacks are infeasible even in white-box environments; however, this proved not to be the case. In particular, Billet and others presented a cryptanalysis of WB-AES with 230 time complexity, and Michiels and others generalized it for all substitution-linear transformation ciphers. Recently, a collision-based cryptanalysis was also reported. In this paper, we revisit Chow and others's first WB-AES implementation and present a conditional re-encoding method for cryptanalysis protection. The experimental results show that there is approximately a 57% increase in the memory requirement and a 20% increase in execution speed.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.2
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• pp.171-179
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• 2011

Feistel and SPN are the two main structures in a block cipher. Feistel is a symmetric structure which has the same structure in encryption and decryption, but SPN is not a symmetric structure. Encrypt round function and decrypt round function in SPN structure have three parts, round key addition and substitution layer with S-box for confusion and permutation layer for defusion. Most SPN structure for example ARIA and AES uses 8 bit S-Box at substitution layer, which is vulnerable to Square attack, Boomerang attack, Impossible differentials cryptanalysis etc. In this paper, we propose a SPN which has a symmetric structure in encryption and decryption. The whole operations of proposed algorithm are composed of the even numbers of N rounds where the first half of them, 1 to N/2 round, applies a right function and the last half of them, (N+1)/2 to N round, employs an inverse function. And a symmetry layer is located in between the right function layer and the inverse function layer. The symmetric layer is composed with a multiple simple bit slice involution S-Boxes. The bit slice involution S-Box symmetric layer increases difficult to attack cipher by Square attack, Boomerang attack, Impossible differentials cryptanalysis etc. The proposed symmetric SPN block cipher with bit slice involution S-Box is believed to construct a safe and efficient cipher in Smart Card and RFID environments where electronic chips are built in.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• Journal of Communications and Networks
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• v.18 no.3
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• pp.273-287
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• 2016

White-box cryptography presented by Chow et al. is an obfuscation technique for protecting secret keys in software implementations even if an adversary has full access to the implementation of the encryption algorithm and full control over its execution platforms. Despite its practical importance, progress has not been substantial. In fact, it is repeated that as a proposal for a white-box implementation is reported, an attack of lower complexity is soon announced. This is mainly because most cryptanalytic methods target specific implementations, and there is no general attack tool for white-box cryptography. In this paper, we present an analytic toolbox on white-box implementations of the Chow et al.'s style using lookup tables. According to our toolbox, for a substitution-linear transformation cipher on n bits with S-boxes on m bits, the complexity for recovering the $$O\((3n/max(m_Q,m))2^{3max(m_Q,m)}+2min\{(n/m)L^{m+3}2^{2m},\;(n/m)L^32^{3m}+n{\log}L{\cdot}2^{L/2}\}\)$$, where $m_Q$ is the input size of nonlinear encodings,$m_A$ is the minimized block size of linear encodings, and $L=lcm(m_A,m_Q)$. As a result, a white-box implementation in the Chow et al.'s framework has complexity at most $O\(min\{(2^{2m}/m)n^{m+4},\;n{\log}n{\cdot}2^{n/2}\}\)$ which is much less than $2^n$. To overcome this, we introduce an idea that obfuscates two advanced encryption standard (AES)-128 ciphers at once with input/output encoding on 256 bits. To reduce storage, we use a sparse unsplit input encoding. As a result, our white-box AES implementation has up to 110-bit security against our toolbox, close to that of the original cipher. More generally, we may consider a white-box implementation of the t parallel encryption of AES to increase security.

• The KIPS Transactions:PartC
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• v.9C no.4
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• pp.445-452
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• 2002

In this paper, we suggest the design of 128bit block cipher which is provable security based on mathematics theory. We have derived the 16$\times$16 matrix(i.e.,linear transformation) which is numerous active S-box, and we proved for DC and LC which prove method about security of SPN structure cipher algorithm. Also, the minimum number of active S-box, the maximum differential probabilities and the maximum linear probabilities in round function of 128bit block cipher algorithm which has an effect to DC and LC are derived.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.9
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• pp.4487-4511
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• 2018

A fast image encryption system based on substitution and diffusion was proposed, which includes one covering process, one substitution process and two diffusion processes. At first, Chen's chaotic system together with an external 256-bit long secret key was used to generate the key streams for image encryption, in which the initial values of Chen's chaotic system were regarded as the public key. Then the plain image was masked by the covering process. After that the resulting image was substituted with the disturbed S-Box of AES. Finally, the substituted image was diffused twice with the add-modulo operations as the core to obtain the cipher image. Simulation analysis and comparison results with AES and some existing image cryptosystems show that the proposed image cryptosystem possesses the merits of fast encryption/decryption speed, good statistical characteristics, strong sensitivity and etc., and can be used as a candidate system of network security communication.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.164-167
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• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.