• Journal of IKEEE
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• v.15 no.1
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• pp.57-63
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• 2011

This paper presents a tunable band pass filter (BPF) for multi bio-signal detection. The bandwidth can be controlled by the bias current of transconductance (gm), while conventional BPF exploited switchable capacitor array for band selection. With this design technique, the die area of proposed BPF reduced to at least one tenth the area of conventional design. The simulation results show the high cut-off frequency tuning range of from 100Hz to 1Khz. The circuit was implemented with a 0.18um CMOS standard technology. Total current consumption is 1uA at the supply voltage of 1V with sub-threshold design technique.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.3
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• pp.313-321
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• 2009

This paper describes the downlink design of a transportable small-sized KOMPSAT ground station using sub-carrier signal. Based on the analysis of the transmission modes of satellite real-time telemetry and range measurement signals, the downlink channel design of KOMPSAT ground station using sub-carrier signal was processed. By considering the threshold signal-to-noise ratio of real-time 2 kbps telemetry signal and the required signal-to-noise ratio for satellite range measurement, the small-sized KOMPSAT downlink channel with G/T value of 6.5 dB/K was designed. The real G/T of implemented ground station was proven to be 6.62 dB/K when measured using the Sun. Moreover, through interface test with KOMPSAT, the ground station has shown the required link performance for real-time telemetry acquisition using sub-carrier and was consequently evaluated to be adequate for a transportable small-sized KOMPSAT ground station.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.887-890
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• 2005

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin updoped Si channel for SCEs control, are being validated for sub-20nm scaling, A channel effects such as the subthreshold swing(SS), and the threshold voltage roll-off(${\Delta}V_{th}$). The propsed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.449-452
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• 2010

We have analyzed channel doping and dimensions(channel length, width and thickness) for the optimum subthreshold characteristics of DG(Double Gate) MOSFET based on the model of MicroTec 4.0. Since the DGMOSFET is the candidate device to shrink short channel effects, the determination of design rule for DGMOSFET is very important to develop sub-100nm devices for high speed and low power consumption. As device size scaled down, the controllability of dimensions and oxide thickness is very low. We have analyzed the short channel effects for the variation of channel dimensions, and found the design conditions of DGMOSFET having the optimum subthreshold characteristics for digital applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.647-654
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• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

• Geomechanics and Engineering
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• v.37 no.4
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• pp.323-339
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• 2024

If the pressure exerted on the face of a tunnel excavated by TBM exceeds a threshold, it leads to failure of the soil or rock masses ahead of the tunnel face, which results in heaving the ground surface. In the current research, the upper bound method of limit analysis was employed to calculate the blow-out pressure of tunnels excavated in rock masses obeying the Hoek-Brown nonlinear criterion. The results of the proposed method were compared with three-dimensional finite element models, as well as the available methods in the literature. The results show that when σ_ci, m_i, and GSI increase, the blow-out pressure increases as well. By doubling the tunnel diameter, the blow-out pressure reduces up to 54.6%. Also, by doubling the height of the tunnel cover and the surcharge pressure exerted on the ground surface above the tunnel, the blow-out pressure increased up to 74.9% and 5.4%, respectively. With 35% increase in the unit weight of the rock mass surrounding the tunnel, the blow-out pressure increases in the range of 14.8% to 19.6%. The results of the present study were provided in simple design graphs that can easily be used in practical applications in order to obtain the blow-out pressure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

• Current Optics and Photonics
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• v.3 no.6
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• pp.583-589
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• 2019

We report experimental results on 940-nm 350-mW AlGaAs/InGaAs transverse single-mode laser diodes (LDs) adopting graded-index separate confinement heterostructures (GRIN-SCH) and p,n-clad asymmetric structures, with improved temperature and small-divergence beam characteristics under high-output-power operation, for a three-dimensional (3D) motion-recognition sensor. The GRIN-SCH design provides good carrier confinement and prevents current leakage by adding a grading layer between cladding and waveguide layers. The asymmetric design, which differs in refractive-index distribution of p-n cladding layers, reduces the divergence angle at high-power operation and widens the transverse mode distribution to decrease the power density around emission facets. At an optical power of 350 mW under continuous-wave (CW) operation, Gaussian narrow far-field patterns (FFP) are measured with the full width at half maximum vertical divergence angle to be 18 degrees. A threshold current (I_th) of 65 mA, slope efficiency (SE) of 0.98 mW/mA, and operating current (I_op) of 400 mA are obtained at room temperature. Also, we could achieve catastrophic optical damage (COD) of 850 mW and long-term reliability of 60℃ with a TO-56 package.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.1-8
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• 2013

This paper presents a variable gain amplifier(VGA) without passive devices. This VGA employes the architecture of current feedback amplifier and variable gain can be achieved by using the GM ratios of two trans-conductance(gm) circuits. To obtain linearity and high gain, it uses current division technique and source degeneration in feedback GM circuits. Input trans-conductance(GM) circuit was biased by using a tunable voltage controller to obtain variable gain. The prototype of the VGA is designed in $0.35{\mu}m$ CMOS technology and it is operating in sub-threshold region for low power consumption. The the gain of proposed VGA is varied from 23dB to 43dB, and current consumption is $2.82{\mu}A{\sim}3{\mu}A$ at 3.3V. The area of VGA is 1$120{\mu}m{\times}100{\mu}m$.