• 제목/요약/키워드: sub-pixel operation

검색결과 15건 처리시간 0.021초

과도상태 시뮬레이션을 사용한 OLED 픽셀 회로의 신뢰성 분석 방안 연구 (Study on the Reliability of an OLED Pixel Circuit Using Transient Simulation)

  • 정태호
    • 반도체디스플레이기술학회지
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    • 제20권4호
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    • pp.141-145
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    • 2021
  • The brightness of the Organic Light Emitting Diode (OLED) display is controlled by thin-film transistors (TFTs). Regardless of the materials and the structures of TFTs, an OLED suffers from the instable threshold voltage (Vth) of a TFT during operation. When designing an OLED pixel with circuit simulation tool such as SPICE, a designer needs to take Vth shift into account to improve the reliability of the circuit and various compensation methods have been proposed. In this paper, the effect of the compensation circuits from two typical OLED pixel circuits proposed in the literature are studied by the transient simulation with a SPICE tool in which the stretched-exponential time dependent Vth shift function is implemented. The simulation results show that the compensation circuits improve the reliability at the beginning of each frame, but Vth shifts from all TFTs in a pixel need to be considered to improve long-time reliability.

H.264 움직임 예측을 위한 Luma와 Chroma 부화소 보간기 설계 (Design of Luma and Chroma Sub-pixel Interpolator for H.264 Motion Estimation)

  • 이선영;조경순
    • 정보처리학회논문지A
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    • 제18A권6호
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    • pp.249-254
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    • 2011
  • 본 논문은 H.264 움직임 예측을 위해 휘도 성분과 색차 성분의 부화소를 생성하는 효율적인 부화소 보간기 회로 설계에 대해 기술한다. 제안된 구조를 기반으로 한 회로는 보간 연산을 위해 입력 데이터를 버퍼링하지 않고 수평, 수직, 대각선의 부화소 보간을 병렬로 처리한다. 휘도성분에 대한 1/2 화소, 1/4 화소 보간과 색차 성분에 대한 1/8 화소 보간을 동시에 처리하여 회로 성능을 더욱 개선하였다. 회로 크기를 줄이기 위해 본 논문에서는 병렬로 보간 연산을 처리하는데 필요한 모든 중간 데이터를 레지스터 대신 내부 SRAM에 저장하였다. 제안된 구조를 레지스터 전달 수준의 회로로 기술하였고, FPGA 보드에서 동작을 검증하였다. 또한 구현된 회로를 130nm CMOS 표준 셀 라이브러리를 이용하여 게이트 수준의 회로로 합성하였다. 합성된 회로의 크기는 20,674 게이트이고 최대 동작 주파수는 244MHz이다. 회로에 사용된 SPSRAM의 전체 크기는 3,232 비트이다. 구현된 회로는 논리 게이트와 SRAM을 포함하여 다른 논문에서 제안한 회로에 비해 크기가 작고 성능도 우수하다.

제지공정의 실시간 결함 검출을 위한 영상 기반 웹 검사 시스템 (A Video based Web Inspection System for Real-time Detection of Paper Defects during Papermaking Processes)

  • 한종우;최영규
    • 반도체디스플레이기술학회지
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    • 제9권2호
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    • pp.79-85
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    • 2010
  • In this paper, we propose a web inspection system (WIS) for real-time detection of paper defects which can cause critical fractures during papermaking process. Our system incorporates high speed line-scan camera, lighting system, and detection algorithm to provide robust and precise detection of paper defects in real-time. Since edge defects are very crucial to the paper fractures, our system focuses on the edge region of the paper instead of inspecting the whole paper area. In our algorithm, image projection and sub-pixel operation are utilized to detect the edge defects precisely and connected component labeling and shape analysis techniques are adopted to extract various kinds of the region defects. Experimental results revealed that our web inspection system is very efficient for detecting paper defects during papermaking processes.

4K-UHD 영상을 지원하는 실시간 통합 복호기용 부화소 보간 회로 설계 (Design of Sub-pixel Interpolation Circuit for Real-time Multi-decoder Supporting 4K-UHD Video Images)

  • 이수정;조경순
    • 전기전자학회논문지
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    • 제19권1호
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    • pp.1-9
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    • 2015
  • 본 논문은 4K-UHD 영상 크기를 지원하는 실시간 통합 복호기용 부화소 보간 회로를 제안한다. 제안하는 통합부화소 보간 회로는 H.264, MPEG-4, VC-1과 새로운 동영상 압축 표준인 HEVC를 지원한다. 회로의 면적을 줄이기 위해 각 표준에 해당하는 보간 알고리즘의 공통되는 부분을 공유하였다. 또한 회로의 저면적과 성능의 최적화를 위해 중간 버퍼를 효율적으로 사용하였다. 제안하는 통합 부화소 보간 회로를 130nm 표준 셀 라이브러리를 이용하여 합성한 결과, 회로의 크기는 122,564 게이트이고, 최대 동작 주파수 200MHz에서 4K-UHD 영상을 초당 35~86 프레임 속도로 처리한다. 따라서 제안하는 회로는 4K-UHD 영상을 실시간으로 처리할 수 있다.

Pipe-line 구조를 갖는 Video Encoder 구현에 관한 연구 (A Study on Video Encoder Implementation having Pipe-line Structure)

  • 이인섭;이완범;김환용
    • 한국컴퓨터산업학회논문지
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    • 제2권9호
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    • pp.1183-1190
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    • 2001
  • 본 논문에서는 아날로그의 비디오 신호를 디지털로 부호화하는데 기존과 다른 파이프라인 방식을 사용하도록 하였다. 부호화기의 전체 동작을 화소 클럭비에 따른 파이프라인 구조로 설계하여 각 하위 블록들의 동작 타이밍을 확보하여 시스템을 안정화시켰으며 고정된 계수와 곱셈의 경우 기존의 ROM 테이블 또는 곱셈기 방식을 사용하지 않고 쉬프트와 덧셈기 방식으로 설계함으로써 시스템의 복잡도를 줄이며 논리 게이트 수를 15%줄이는 효과를 보였다. 설계된 부호화기는 각각의 하위 블록으로 나누어 VHDL로 설계하였고, Max+plusII를 이용한 FPGA로 동작 확인을 하였다.

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파이프라인 구조를 갖는 비디오 부호화기 설계에 관한 연구 (A Study on Video Encoder Design having Pipe-line Structure)

  • 이인섭;이선근;박규대;박형근;김환용
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
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    • pp.169-172
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    • 2001
  • In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

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종이컵 내면불량 검사를 위한 영상처리 알고리즘 응용에 관한 연구 (A Study on the Application of Image Processing Algorithm for Paper-cup Inner Defect Inspection)

  • 엄기복;김용;이규훈;권순도;윤석호
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 하계학술대회 논문집 D
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    • pp.2521-2524
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    • 2002
  • In this paper, We propose an Image processing algorithm for a paper-cup inner defect inspection. First, we devide a cup image to four sections considering the characteristic of a cup and filter noises limit by using the flood-fill algorithm and median filter. Second, to obtain the clearer inspection result of the edge point inner cup, We apply the sharpening convolution filer to the objected inspect the edge points by using the LOG edge detector. Third, executing sub-pixel operation with the orignal image, we find the defect parts in the cup. Finally, denoting the inspected defect parts as rectangular, we recompose the images of the defected ones.

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In-line Critical Dimension Measurement System Development of LCD Pattern Proposed by Newly Developed Edge Detection Algorithm

  • Park, Sung-Hoon;Lee, Jeong-Ho;Pahk, Heui-Jae
    • Journal of the Optical Society of Korea
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    • 제17권5호
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    • pp.392-398
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    • 2013
  • As the essential techniques for the CD (Critical Dimension) measurement of the LCD pattern, there are various modules such as an optics design, auto-focus [1-4], and precise edge detection. Since the operation of image enhancement to improve the CD measurement repeatability, a ring type of the reflected lighting optics is devised. It has a simpler structure than the transmission light optics, but it delivers the same output. The edge detection is the most essential function of the CD measurements. The CD measurement is a vital inspection for LCDs [5-6] and semiconductors [7-8] to improve the production yield rate, there are numbers of techniques to measure the CD. So in this study, a new subpixel algorithm is developed through facet modeling, which complements the previous sub-pixel edge detection algorithm. Currently this CD measurement system is being used in LCD manufacturing systems for repeatability of less than 30 nm.

지역적 이진패턴을 이용한 2차원 바코드 검출 알고리즘 (A 2-D Barcode Detection Algorithm based on Local Binary Patterns)

  • 최영규
    • 반도체디스플레이기술학회지
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    • 제8권2호
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    • pp.23-29
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    • 2009
  • To increase the data capacity of one-dimensional symbology, 2D barcodes have been proposed a decade ago. In this paper, a new 2D barcode detection algorithm based on Local Binary Pattern is presented. To locate 2D barcode symbols, a texture analysis scheme based on the Local Binary Pattern is adopted, and a gray-scale projection with sub-pixel operation is utilized to separate the symbol precisely from the input image. Finally, the segmented symbol is normalized using the inverse perspective transformation for the decoding process. The proposed method ensures high performances under various lighting/printing conditions and strong perspective deformations. Experiments show that our method is very robust and efficient in detecting the symbol area for the various types of 2D barcodes.

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Conjugate Point Extraction for High-Resolution Stereo Satellite Images Orientation

  • Oh, Jae Hong;Lee, Chang No
    • 한국측량학회지
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    • 제37권2호
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    • pp.55-62
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    • 2019
  • The stereo geometry establishment based on the precise sensor modeling is prerequisite for accurate stereo data processing. Ground control points are generally required for the accurate sensor modeling though it is not possible over the area where the accessibility is limited or reference data is not available. For the areas, the relative orientation should be carried out to improve the geometric consistency between the stereo data though it does not improve the absolute positional accuracy. The relative orientation requires conjugate points that are well distributed over the entire image region. Therefore the automatic conjugate point extraction is required because the manual operation is labor-intensive. In this study, we applied the method consisting of the key point extraction, the search space minimization based on the epipolar line, and the rigorous outlier detection based on the RPCs (Rational Polynomial Coefficients) bias compensation modeling. We tested different parameters of window sizes for Kompsat-2 across track stereo data and analyzed the RPCs precision after the bias compensation for the cases whether the epipolar line information is used or not. The experimental results showed that matching outliers were inevitable for the different matching parameterization but they were successfully detected and removed with the rigorous method for sub-pixel level of stereo RPCs precision.