• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.287-288
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• 2005

In this study, we have investigated electro-optical characteristics of thermal and UV stressed TN cells on the rubbed polyimide surface. Mono-domain alignments of thermal stressed TN cells over temperature of liquid crystal isotropic phase were almost same that of no thermal stressed TN cells. Also, threshold voltage and response time of thermal stressed TN cells were same that of no thermal stressed TN cells. Finally, the residual DC voltage of the thermal stressed TN cell on the polyimide surface show decrease of characteristics as increasing thermal stress time. Therefore, thermal stability of TN cell was decreased by high thermal stress for the long times.

• Transactions on Electrical and Electronic Materials
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• 제10권1호
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• pp.5-8
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• 2009

The reliability of multilayer ceramic capacitor with active thin dielectric layer was investigated by highly accelerated life test at various stress condition. The distribution of multilayer ceramic capacitor failure times is plotted as a function of time from Weibull distribution function. According to the test result, voltage acceleration factor is obtained from 2.24 to 2.96. The acceleration by temperature is much higher than other values of active thick dielectric layer. It is clear that median time to failure is affected by the stress voltage for high volumetric efficiency ceramic capacitors with active thin dielectric layer. The degradation under stress of voltage involves electromigration and accumulation of oxygen vacancy at Ni electrode interface of cathode.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.343-346
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• 1998

Degradation characteristics of the Pr-based ZnO varistor with $Y_2O_3$content (0.0-4.0 mol!%j were investigated. It was appeared that the variation of the J-E characteristics in the reverse direction before and after the applied stress with increasing $Y_2O_3$ content was larger than that of the forward direction but the variation was extrernly small. For all varistor, the leakage current with the stress time during the applied stress somewhat increased initialy but afterthat was almost constant or slightly decreased. The overall varistor voltage and nonlinear coefficient were less than 5%. Especially, in the case of Pr-based ZnO varistor containing 2.0 mol% to 4.0 mol% $Y_2O_3$, the variation of breakdown voltage and nonlinear coefficient was less than 1% and 5%. respectively. As a result, they showed good stability.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.180-185
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• 2017

In this research, we proposed the simple and efficient method to calculate the shear stresses by using the mid-point measurements in ${\pm}45^{\circ}$ semiconductor resistor-sensor pair. Compared to the previous works, the measurements became much simpler by combining the approximation theory with the technique of mid-point measurement. In addition, we proposed another novel method for the stress calculation in which we could increase the sensitivity of the stress sensor by controlling the applied voltage between the sensor-pair. For the applied voltage of 8 V, the sensitivity showed a significant increase by 100%.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.408-411
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• 2004

The electrical stability against surge stress of ZPCCY-based varistors were investigated at different sintering times. Sintering time decreased the varistor voltage and nonlinear exponent from 279.6 to 179.1 and from 52.5 to 24.9, respectively. On the contrary, the leakage current and dielectric dissipation factor increased from 1.2 to 9.8 ${\mu}A$ and from 0.0461 to 0.0651 with increase of sintering time. For all varistors, the variation rates of V-I characteristic parameters against surge stress were affected in order of varistor voltage$\rightarrow$nonlnear exponent$\rightarrow$leakage current. On the whole, the electrical stability against surge stress increased with increasing sintering time. Conclusively, it is assumed that the varistor sintered for 2 h exhibited comparatively good characteristics, in view of overall characteristics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.324-327
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• 2000

In this paper, the effects of negative and positive bias stress on p-channel poly-Si TFT's fabricated by excimer laser annealing have been investigated After positive and negative bias stress, transcon-ductance(g$_{m}$) is increased because of a reduction of the effective channel length due to the injected electron in the gate oxide. In the positive bias stress, the injection of hole is appeared after stress time of 3600sec and g$_{m}$ is decreased. On the other hand, the gate voltage at the maximum g$_{m}$, S-swing and threshold voltage(V$_{th}$) are decreased because of the interface state generation due to the injection of electrons into the gate oxide.e.ide.e.

• Journal of Power Electronics
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• 제9권6호
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• pp.823-834
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• 2009

This paper proposes a high-efficiency single-stage ac/dc converter. The proposed converter features low voltage stresses and reduced switching losses. It operates at the boundary of discontinuous- and continuous-conduction modes by employing variable switching frequency control. The turn-on switching loss of the switch can be reduced by turning it on when the voltage across it is at a minimum. The voltage across the bulk capacitor is independent of the output loads and maintained within the practical range for the universal line input, so the problem of high voltage stress across the bulk capacitor is alleviated. Moreover, the voltage stress of the output diodes is clamped to the output voltage, and the output diodes are turned off at zero-current. Thus, the reverse-recovery related losses of the output diodes are eliminated. The operational principles and circuit analysis are presented. A prototype circuit was built and tested for a 150 W (50V/3A) output power. The experimental results verify the performance of the proposed converter.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제5B권1호
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• pp.43-49
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• 2005

The high rate of voltage rise (dv/dt) in motor terminals caused by high-frequency switching and impedance mismatches between inverter and motor are known as the primary causes of irregular voltage distributions and insulation breakdowns on stator windings in IGBT PWM inverter-driven induction motors. In this paper, voltage distributions in the stator windings of an induction motor driven by an IGBT PWM inverter are studied. To analyze the irregular voltages of stator windings, high frequency parameters are derived from the finite element (FE) analysis of stator slots. An equivalent circuit composed of distributed capacitances, inductance, and resistance is derived from these parameters. This equivalent circuit is then used for simulation in order to predict the voltage distributions among the turns and coils. The effects of various rising times in motor terminal voltages and cable lengths on the stator voltage distribution are also presented. For a comparison with simulations, an induction motor with taps in the stator turns was made and driven by a variable-rising time switching surge generator. The test results are shown.

• Journal of Power Electronics
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• 제19권5호
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• pp.1108-1121
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• 2019

The non-inverting buck-boost converter (NIBB) is a step-up and step-down DC-DC converter suitable for wide-input-voltage-range applications. However, when the input voltage is close to the output voltage, the NIBB needs to operate in the buck-boost mode, causing a significant efficiency reduction since all four switches operates in the PWM mode. Considering both the current stress limitation and the efficiency optimization, a novel design methodology for the optimal phase-shift modulation of a NIBB in the buck-boost mode is proposed in this paper. Since the four switches in the NIBB form two bridges, the shifted phase between the two bridges can serve as an extra degree of freedom for performance optimization. With general phase-shift modulation, the analytic current expressions for every duty ratio, shifted phase and input voltage are derived. Then with the two key factors in the NIBB, the converter efficiency and the switch current stress, taken into account, an objective function with constraints is derived. By optimizing the derived objective function over the full input voltage range, an offline design methodology for the optimal modulation scheme is proposed for efficiency optimization on the premise of current stress limitation. Finally, the designed optimal modulation scheme is implemented on a DSPs and the design methodology is verified with experimental results on a 300V-1.5kW NIBB prototype.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.2031-2039
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• 2015

In the LED lighting industry, the dimming function in the LED lamp is required by demands of many consumers. To drive this LED lighting, various types of power converters have been applied. Among them, an LLC resonant converter could be applied for high power LED lighting because of its high efficiency and high power density, etc. The function of power factor correction (PFC) might be added to it. In this paper, a dimmable single-stage asymmetrical LLC resonant converter is proposed. The proposed converter performs both input-current harmonics reduction and PFC using the discontinuous conduction mode (DCM). Also, the lower voltage stress across switching devices as well as the zero voltage switching (ZVS) in switching devices is realized by the proposed topology. It can reduce cost and has high efficiency of the driver. In addition, the regulation of the output power by variable switching frequency can vary the brightness of a light. In the proposed converter, one of the attractive advantages doesn’t need any extra control circuits for the dimming function. To verify the performance of the proposed converter, simulation and experimental results from a 300W prototype are provided.