• International Journal of Internet, Broadcasting and Communication
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• 제8권3호
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• pp.12-24
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• 2016

Recently, as the price per bit is decreasing at a fast rate, flash memory is considered to be used as primary storage of large-scale database systems. Although flash memory shows off its high speeds of page reads, however, it has a problem of noticeable performance degradation in the presence of increasing update workloads. When updates are requested for pages with random page IDs, in particular, the shortcoming of flash tends to impair significantly the overall performance of a flash-based database system. Therefore, it is important to have a way to efficiently update the B+-tree, when it is stored in flash storage. This is because most of updates in the B+-tree arise at leaf nodes, whose page IDs are in random. In this light, we propose a new flash B+-tree that stores up-to-date versions of leaf nodes in sibling-leaf blocks (SLBs), while updating them. The use of SLBs improves the update performance of B-trees and provides the mechanism for fast key range searches. To verify the performance advantages of the proposed flash B+-tree, we developed a mathematical performance evaluation model that is suited for assessing B-tree operations. The performance comparisons from it show that the proposed flash B+-tree provides faster range searches and reduces more than 50% of update costs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.781-792
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• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2000년도 가을 학술발표논문집 Vol.27 No.2 (1)
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• pp.210-212
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• 2000

In this paper, we present a comcurrency control scheme over the index structure in main memory databases using multiversion mechanism, and implement it on T-tree. As a well-known idea for comcurrency control, multiversion allows multiple transactions to reat and write different versions of the same data item, each transaction sees a consistent set of versions for all the data items it accesses[1]. Logical versioning and physical versioning techniques are used to keep versions of data item and versions of index node respectively. The main features of this multiversion indexing approach are (1)update operations and rotations on T-tree can take place concurrently, (2)the number of locking and latching requirement is sharply reduced because read-only transactions do not obtain any locks or latches and update transactions obtain latches only when actually performing the update, (3)it reduces storage overhead for tracking version and reclaims storage in time, and (4)it provides complete isolation of read-only transactions from update transactions, so the read-only transactions can get response information without any block.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권8호
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• pp.3203-3215
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• 2015

Due to the high growth of SNS population, service scalability is one of the critical issues to be addressed. The cloud environment provides the flexible computing and storage resources for services deployment, which fits the characteristics of scalable SNS deployment. However, if the SNS related information is not properly placed, it will cause unbalance load and heavy transmission cost on the storage virtual machine (VM) and cloud data center (CDC) network. In this paper, we characterize the SNS into a graph model based on the users' associations and interest correlations. The node weight represents the degree of associations, which can be indexed by the number of friends or data sources, and the link weight denotes the correlation between users/data sources. Then, based on the SNS graph, the two-step algorithm is proposed in this paper to determine the placement of SNS related data among VMs. Two k-means based clustering schemes are proposed to allocate social data in proper VM and physical servers for pre-configured VM and dynamic VM environment, respectively. The experimental example was conducted and to illustrate and compare the performance of the proposed schemes.

• 한국통신학회논문지
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• 제40권9호
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• pp.1734-1740
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• 2015

본 논문은 분산 저장 시스템에서 기존의 부분접속수를 일반화한 개념인 결합 부분접속수를 소개하고, 결합 부분접속수($r_1$=2, $r_2$=3 or 4)를 만족하는 부호 설계 방식을 제안한다. 결합 부분접속수란 다양한 수의 노드 손실을 복구하기 위해 필요한 노드 수 집합을 의미한다. 제안된 방식은 완전다분할그래프를 사용하여 부호 설계를 단순화한다. 또한 제안된 방식으로 임의의 양의 정수 t에 대해 (2,t)-가용도를 갖는 이진 부분접속복구 부호를 설계할 수 있다. 즉, 1개 노드 손실 시 t개의 서로소인 복구 집합으로부터 각각 복구가 가능하며, 이때 각 복구 집합의 크기는 최대 2이다. 이러한 성질은 핫 데이터의 병렬처리를 가능하게 하므로 분산 저장 시스템에서 중요한 의미를 갖는다.

• 한국정보과학회논문지:데이타베이스
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• 제33권3호
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• pp.342-352
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• 2006

최근의 XML 저장소에 관한 연구들은 기존의 데이타 저장을 위해 주로 사용해 왔던 관계형 데이타베이스에 효율적으로 XML 데이타를 매핑하는 기법이나 XML 데이타를 위한 새로운 전용 저장소에 대한 연구들이 주를 이룬다. XML 전용 저장소에서 많이 사용되는 방식으로 XML 문서를 파싱하여 각 노드들을 개별적인 객체로 생성한 후 이를 저장하는 방식이 있다. 이러한 저장 방식에서는 개별적인 객체들의 물리적 배치, 즉 클러스터링이 성능에 영향을 미칠 수 있다. 본 논문에서는 하나의 XML 문서를 보다 효율적으로 저장하는 클러스터링 기법을 제안한다. 제안하는 기법은 데이타 노드들의 경로 유사도를 기반으로 클러스터링을 수행하여 질의 요청에 대한 결과를 반환할 때 발생하는 페이지 I/O를 줄인다. 또한 경로 질의 처리시 필요한 클러스터만을 이용하여 질의 처리를 수행하는 방법을 제안한다. 이는 질의 처리과정에서 불필요한 데이타를 제외함으로써 결과적으로 탐색 공간의 크기를 줄일 수 있어 보다 효율적인 경로 질의 처리를 가능하게 한다. 이밖에 본 논문에서는 기존의 다른 클러스터링 기법들과 제안한 기법들과의 성능 비교를 수행하고, 이를 통해 적절한 클러스터링 기법을 이용하면 XML 저장소의 성능을 향상시킬 수 있음을 보인다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제8권11호
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• pp.3916-3936
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• 2014

Smartphone applications like games, image processing, e-commerce and social networking are gaining exponential growth, with the ubiquity of cellular services. This demands increased computational power and storage from mobile devices with a sufficiently high bandwidth for mobile internet service. But mobile nodes are highly constrained in the processing and storage, along with the battery power, which further restrains their dependability. Adopting the unlimited storage and computing power offered by cloud servers, it is possible to overcome and turn these issues into a favorable opportunity for the growth of mobile cloud computing. As the mobile internet data traffic is predicted to grow at the rate of around 65 percent yearly, even advanced services like 3G and 4G for mobile communication will fail to accommodate such exponential growth of data. On the other hand, developers extend popular applications with high end graphics leading to smart phones, manufactured with multicore processors and graphics processing units making them unaffordable. Therefore, to address the need of resource constrained mobile nodes and bandwidth constrained cellular networks, the computations can be migrated to resourceful servers connected to cloud. The server now acts as a bridge that should enable the participating mobile nodes to offload their computations through Wi-Fi directly to the virtualized server. Our proposed model enables an on-demand service offloading with a decision support system that identifies the capabilities of the client's hardware and software resources in judging the requirements for offloading. Further, the node's location, context and security capabilities are estimated to facilitate adaptive migration.

• 한국콘텐츠학회논문지
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• 제12권7호
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• pp.21-28
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• 2012

데이터 중심 저장 기법(DCS)은 무선 센서 네트워크에서 수집된 데이터를 효율적으로 저장하고 관리하기 위한 대표적인 연구이다. DCS 기법에서는 발생하는 데이터를 값에 따라 저장을 담당하는 노드들이 할당되어 있다. 이러한 특성으로 인해 노드의 결함에 매우 취약하다는 문제점이 있다. 본 논문은 DCS 환경에서 노드 결함에 의한 데이터 소실이 발생하였을 경우, C-Point(Character-Point)기반 근사 복구 기법을 제안한다. 제안하는 기법은 물리 데이터의 공간 연속성을 이용하여 소실 데이터를 복구하여 질의 결과의 정확도를 높인다. 제안하는 기법의 우수성을 보이기 위해 결함이 발생하는 DCS 환경에서 시뮬레이션을 수행하였다. 성능평가 결과, 약 2.5%의 에너지 소모량 증가를 통해 정확도를 약 28% 향상시켰다.

• 한국지진공학회:학술대회논문집
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• 한국지진공학회 2000년도 춘계 학술발표회 논문집 Proceedings of EESK Conference-Spring
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• pp.427-434
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• 2000

This paper presents a computer program for a 2-D fluid-structure-soil interaction analysis. With this computer program the fluid can be modeled by a spurious free 4-node displacement-based fluid element which uses rotational penalty and mass projection technique in conjunction with the one point reduced integration scheme to remove the spurious zero energy modes. The structure and near field soil are discretized by the standard finite elements while the unbounded far field soil are discretized by the standard finite elements while the unbounded far field soil is represented by the frequency dependent dynamic infinite elements. Sine this method models directly the fluid-structure-soil system it can be applied to the dynamci analysis of 2-D liquid storage structure with complex geometry. For the purpose of verification dynamic analyses for tanks on a rigid foundation and on compliant embankment are carried out. Comparison of the present results with those by ANSYS program shows good agreement.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.