• Transactions of Materials Processing
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• v.23 no.2
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• pp.88-94
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• 2014

The under-drive brake piston is an essential part in the automatic transmissions of automobiles. This component is manufactured by forging after blanking from S55C plate with a thickness of 6mm. It is difficult to design the plate forging process using a thick plate approach since there will be limited material flow as well as large press loads. Furthermore, the under-drive brake piston has a complex shape with a right angle step, which often results in die unfill and abrupt increase in press load. To overcome these obstacles, a separate die for filling material sufficiently to the corner of the right angle step is proposed. However, this approach induces an uncontrolled workpiece surface between the dies, resulting in flash. This excess flash degrades the tool life in the final machining after cold forging as well as increases the cycle time to obtain the net-shape of the part. In the current study, we propose an optimum process design using a conventional die shaped with the benefit of finite element analysis. This approach enhanced the process efficiency without sacrificing the dimensional accuracy in the forged part. As the result, the optimum plate forging process was done with a two stage die, which reduces weight of by 6% compared with previous process for the under-drive brake piston.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.41-41
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• 2006

Step and Flash Imprint Lithography is an interesting low cost alternative to traditional microlithographic processes that offers the ability to efficiently produce nanostructures at unprecedented resolution. New photopolymerizable formulations are required to enable this process. This paper will describe progress in the design and development of acrylate and vinyl ether based platforms for this application together with efforts to prepare photopolymerizable, thermally stable, magterials with low dielectric constants for use in an efficient new method for fabricating the interconnect structures in microprocessors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.12-12
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• 2004

나노임프린트 관련되어 전 세계적으로 지금까지 4개회사가 장비 및 공정기술 개발을 하고 있으나 대부분 수년 전에 창업한 회사이며, 4개의 나노임프린트 장비 관련 회사는 미국의 Nanonex, 오스트리아의 EVG사, 미국의 Molecular Imprint Inc. (MII),스웨덴이 Obducat이다. 개발된 장비의 대부분은 수작업이 필요한 연구용 장비로 현재 공정 기술개발을 위해 활용되고 있으며, MI사 장비가 최초로 양산 적용을 목표로 개발하여 국내에도 도입 되어있다. 일본에서는 아직 장비 개발이 시도된 바 없으며 현재 관련 공정 기술개발을 하고 있다.(중략)

• Journal of information and communication convergence engineering
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• v.7 no.4
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• pp.507-515
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• 2009

In this paper, we propose an image signal processor (ISP) for an ultra small HD-grade video sensor with 3A (AWB, AE, and AF) in camera phones that can process 720P/30fps videos. In order to enhance the video quality of the systems, it is necessary to achieve the high performance of the 3A. The proposed AWB algorithm multiplies the adjusted coefficients of color gains to the captured data of white objects. The proposed AE method adopts the index step moving based on the difference between an averaged Y luminance and a target luminance, together with IIR filters with variable time responses. The proposed AF technique controls the focus curve to find the lens position that maximizes the integrated high frequency components in luminance values by using highpass filters. Finally, we compare the image quality captured from our system to the quality of a commercial HD camcorder in order to evaluate the performance of the proposed ISP. The proposed ISP system is also fabricated with 0.18um CMOS flash memory process.

• Journal of Microbiology and Biotechnology
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• v.12 no.3
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• pp.522-525
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• 2002

A very rapid and efficient separation technique for cellular rhizobial cyclosophoraoses was developed based on fractional precipitation and partition chromatography. Cyclosophoraoses are known to function in the osmotic regulation and root nodule formation of legumes during the nitrogen fixation process. Cyclosophoraoses are produced as unbranched cyclic (1longrightarrow12)-${\beta}$-D-glucans in Agrobacterium or Rhizobium species. Recent research has shown that cyclosophoraoses can form inclusion complexation with various unstable or insoluble guest chemicals, thereby implying great potential for industrial application. Typical separation of pure cellular cyclosophoraoses has been so far carried out by several time-consuming steps, including size exclusion, anion exchange, and desalting liquid chromatographies, with a relatively poor recovery. However, the proposed method demonstrated that the successive application of fractional ethanol precipitation and one step of silica gel-based flash column chromatography was enough to simultaneously purify neutral or anionic forms of cyclosophoraoses. This novel technique is very rapid and provides a high recovery.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.3
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• pp.359-363
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• 2011

An orthogonal magnetic field is often used for a military vessel in the deperm process such as Flash D deperm protocol and Anhysteretic deperm protocol. The effect of the orthogonal magnetic field on a deperm performance was investigated for a sample with strain-induced magnetization and field-induced magnetization given to different direction. A 70mm wide, 110mm long and 0.25mm thick rectangular steel plate was bent to have U-shape and to generate a strong strain on the bottom region of U-shaped steel plate. Field-induced magnetization was attached by NdFeB permanent magnet. Demagnetization was performed by applying magnetic field with a step decrement from the first field(the first shot) under the action of DC bias field.