• Journal of Convergence Society for SMB
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• v.1 no.1
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• pp.75-83
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• 2011

Unified Modeling Language (UML) is widely accepted in industry and particularly UML State Machine Diagram is popular for describing the dynamic behavior of classes. This paper discusses deadlock detection of System using UML State Machine Diagram. Since a State Machine Diagram is used for indivisual class' behavior, all the State Machine Diagrams of the classes in the system are combined to make a big system-wide State Machine Diagram to describe system behavior. Generally this system-wide State Machine Diagram is very complex and contains invalid state and transitions. To make it a usable and valid State Machine Diagram, synchronization and externalization are applied. The reduced State Machine Diagram can be used for describing system behavior thus conventional model-checking technique can be applied. This paper shows how deadlock detection of system can be applied with simple examples. All the procedures can be automatically done in the tool.

• The KIPS Transactions:PartD
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• v.16D no.4
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• pp.527-540
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• 2009

State diagrams describe the dynamic behavior of an individual object as a number of states and transitions between these states. In this paper, we propose an automated technique to the generation of a state diagram from class operations with pre/post conditions. And I also develop a supporting tool, SDAG (State Diagram Automatic Generation tool). Additionally, we propose a complexity metric and a state diagram generation approach concerning types of each operation for decreasing complexity of generated state diagram.

• Proceedings of the KIEE Conference
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• 1985.07a
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• pp.234-237
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• 1985

본 논문은 득정한 하드웨어를 구성함에 앞서 그 시스템이 State-diagram으로 표현된 것을 입력으로 받아 state-diagram이 맞는지를 verify하는 방법을 제시하며 equivalence state를 찾아 reduce해준다. Program의 실현은 Prolog로 하였다.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.1
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• pp.19-26
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• 2013

To improve the reliability and quality of software system, many studies of the testing based on state-transition diagram have been in progress. Existing studies tried to solve the complexity problem of state-transition diagram. But the development of test case demands the better way to derive and manage the state diagram with low complexity. In this paper, the STMT(State-Transition Mapping Tree) is proposed to decrease the complexity of state diagram without changing or loosing the original state or transition information. Comparing with other methods, the proposed method turns out to be less complex.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.11
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• pp.487-494
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• 1986

This paper is concerned with the techniques of error check and reduction of state diagram using logic programming. Error check program aims to check not only syntax errors but also semantic errors. And reduction program optimizes the state diagram by finding the redundant equivalence states and removing those from the set of states. The input of both program is state diagram represented as state table form. The output of error check program is error comment. The output of reduction program is equivalence reduced state table. Both programs are implemented using prolog. Prolog has very powerful pattern matching, and its automatic back-tracking capabilities facilitate easy-to-write error check and reduction programs.

• Journal of applied mathematics & informatics
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• v.27 no.5_6
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• pp.1331-1342
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• 2009

In this paper, we analyze the behavior of the state transition of nongroup CA with a single attractor over GF($2^p$)(p > 1), and propose the algorithm for the construction of the state transition diagram of a Single Attractor CA(SACA) over GF($2^p$) which is very different from the construction algorithm for the state transition diagram of GF(2) SACA.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.31 no.5
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• pp.40-45
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• 2013

• Proceedings of the Korea Society of Design Studies Conference
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• 2001.10a
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• pp.77-77
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• 2001

• Journal of KIISE
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• v.41 no.10
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• pp.774-784
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• 2014

Studies of fault-injection into state machine diagram have been studied for generating robustness test cases. Conventional studies have, however, tended to inject too many faults into diagrams because they only have considered structural aspects of diagrams. In this paper, we propose a method that aims to reduce the number of injected fault without a decrease in effectivenss of robustness test. A proposed method is demonstrated using a microwave oven sate machine diagram and evaluated using a hash table state machine diagram. The result of the evaluation shows that the number of injected faults is decreased by 43% and the number of test cases is decreased by 63% without a decrease in effectiveness of hash table robustness test.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.3
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• pp.161-167
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• 2004

Zone 3 of the distance relay is used to provide the remote back-up protection in case of the failure of the primary protection. However, the risk lot mal-operations under stressed conditions such as heavy loading, voltage and transient instability is usually high. Zone 3 is used in combination with the derivatives of the voltage, and current, etc to prevent mal-operations. Sometimes, the impedance characteristics that restrict the tripping area of relay are used to avoid the mal-operations due to load encroachment. This paper presents a novel Zone 3 scheme based on combining the steady-state components (i.e. 60Hz) and the transient components (TCs) using a state diagram that visualizes the sequence of studies that emanate from the sequence of events. The simulation results show that the novel zone 3 distance relay elements using the proposed method operates correctly for the various events.