• Communications of the Korean Mathematical Society
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• v.33 no.2
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• pp.527-533
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• 2018

Let $\mathcal{X}$ be a countably generated Hilbert module over a locally $C^*$-algebra $\mathcal{A}$ in multiplier module M($\mathcal{X}$) of $\mathcal{X}$. We propose the necessary and sufficient condition such that a sequence $\{h_n:n{{\in}}\mathbb{N}\}$ in M($\mathcal{X}$) is a standard frame of multipliers in $\mathcal{X}$. We also show that if T in $b(L_{\mathcal{A}}(\mathcal{X}))$, the space of bounded maps in set of all adjointable maps on $\mathcal{X}$, is surjective and $\{h_n:n{{\in}}\mathbb{N}\}$ is a standard frame of multipliers in $\mathcal{X}$, then $\{T{\circ}h_n:n{\in}\mathbb{N}}$ is a standard frame of multipliers in $\mathcal{X}$, too.

• Bulletin of the Korean Mathematical Society
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• v.58 no.2
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• pp.461-479
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• 2021

This paper includes a general version of Bessel multipliers in Hilbert C∗-modules. In fact, by combining analysis, an operator on the standard Hilbert C∗-module and synthesis, we reach so-called generalized Bessel multipliers. Because of their importance for applications, we are interested to determine cases when generalized multipliers are invertible. We investigate some necessary or sufficient conditions for the invertibility of such operators and also we look at which perturbation of parameters preserve the invertibility of them. Subsequently, our attention is on how to express the inverse of an invertible generalized frame multiplier as a multiplier. In fact, we show that for all frames, the inverse of any invertible frame multiplier with an invertible symbol can always be represented as a multiplier with an invertible symbol and appropriate dual frames of the given ones.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.1-7
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• 1997

This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.