• 한국초전도ㆍ저온공학회논문지
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• 제9권1호
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• pp.9-13
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• 2007

Coated conductor(CC) is recently in actively progress for the research and development, and its can be used various stabilizer lot the specific requirements for each application. Among various superconducting applications, coated conductor applied to superconducting fault current limiters(SFCLS) bypasses fault current to its stabilizer, where the surge is abruptly reduced ; thus, stainless steel, which has large resistivity can be a suitable stabilizer for SFCLS. Despite high n-value of the YBCO, CC stabilized with stainless steel did not effectively limit the first peak fault current. In the short circuit test results of AMSC's 344S, a half period delay was observed between the fault and the generation of resistance(60Hz). In this paper, we performed short-circuit experiments with stacked and unstacked CC and compared the test results to analyze effective fault current limiting characteristics. we compared time of the generated resistance as the fault current limiting characteristics and made the samples one is the stacked CC and the other is unstacked CC. These samples were used equal numbers of pieces of CC. In addition, comparison and analysis was made for the stacked structure by measuring fault current limiting characteristics with respect to thermal insulation by impregnating with epoxy resin.

• 한국초전도ㆍ저온공학회논문지
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• 제12권3호
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• pp.16-20
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• 2010

For large scale power applications of HTS conductor, it is getting more important to have a stacked HTS coated conductor with low loss and large current capacity. But it was not easy to measure some electric properties. Stabilizer free YBCO CC for striated/ stacked conductors is easily burned out during the measurement of the critical current density because it has no stabilizer and it is difficult to set-up the current lead and voltage taps because it has many pieces of YBCO CC in a conductor. Instead of direct measuring the critical current of a stacked HTS coated conductor, indirect estimation from measuring a magnetization loss of HTS coated conductor could be useful for practical estimation of the critical current. The magnetization loss of a superconductor is supposed to be affected by a full penetrating magnetic field, and it tends to show an inflection point at the full penetrating magnetic field when we generate the graph of magnetization loss vs. external magnetic field. The full penetrating magnetic field depends on the shape of the conductor and its critical current density, so we can estimate the effective critical current density from measuring the magnetization loss. In this paper, to prove the effectiveness of this indirect estimation of the critical current, we prepared several different kinds of YBCO CC(coated conductor) including a stacked conductor short samples and measured the magnetization losses and the critical currents of each sample by using linked pick up coils and direct voltage measurement with transport current respectively.

• 청정기술
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• 제15권2호
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• pp.130-136
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• 2009

상용촉매인 Johnson Matthey사 KATALCO 83-3 촉매를 이용하여 마이크로 채널 반응기 (micro-channel reactor: MCR) 형태에 따른 메탄올 수증기 개질반응을 통한 수소제조반응 특성 연구를 수행하였다. 반응온도 200${\sim}$300$^{\circ}C$, 공간속도 3,000${\sim}$10,000 $hr^{-1}$, 촉매 크기 0.05${\sim}$2.2 mm 조건을 갖는 고정층 반응기에서 반응활성 실험을 수행한 결과, 촉매 크기 0.35 mm에서 최적의 반응활성을 나타났다. 이 결과를 토대로 stacked bed, boat bed 등 마이크로 채널 반응기 형태에 따른 반응활성을 연구한 결과, stacked bed type 마이크로 채널 반응기가 더 좋은 반응활성을 가짐을 알 수 있었다.

• Structural Engineering and Mechanics
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• 제85권4호
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• pp.469-484
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• 2023

A deep recursive bidirectional Cuda Deep Neural Network Long Short Term Memory (Bi-CuDNNLSTM) layer is recruited in this paper to predict the entire force time histories, and the corresponding hysteresis and backbone curves of reinforced concrete (RC) bridge piers using experimental fast and slow cyclic tests. The proposed stacked Bi-CuDNNLSTM layers involve multiple uncertain input variables, including horizontal actuator displacements, vertical actuators axial loads, the effective height of the bridge pier, the moment of inertia, and mass. The functional application programming interface in the Keras Python library is utilized to develop a deep learning model considering all the above various input attributes. To have a robust and reliable prediction, the dataset for both the fast and slow cyclic tests is split into three mutually exclusive subsets of training, validation, and testing (unseen). The whole datasets include 17 RC bridge piers tested experimentally ten for fast and seven for slow cyclic tests. The results bring to light that the mean absolute error, as a loss function, is monotonically decreased to zero for both the training and validation datasets after 5000 epochs, and a high level of correlation is observed between the predicted and the experimentally measured values of the force time histories for all the datasets, more than 90%. It can be concluded that the maximum mean of the normalized error, obtained through Box-Whisker plot and Gaussian distribution of normalized error, associated with unseen data is about 10% and 3% for the fast and slow cyclic tests, respectively. In recapitulation, it brings to an end that the stacked Bi-CuDNNLSTM layer implemented in this study has a myriad of benefits in reducing the time and experimental costs for conducting new fast and slow cyclic tests in the future and results in a fast and accurate insight into hysteretic behavior of bridge piers.

• 전기전자학회논문지
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• 제28권2호
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• pp.234-238
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• 2024

본 논문은 낮은 구동 전류 특성과 3차원 적층 구조로 확장시킬 수 있는 장점을 가진 3차원 적층형 이중 팁 RRAM을 CNN 가속기 아키텍처에 접목하는 연구를 수행한 논문이다. 3차원 적층형 이중 팁을 적층 형태의 병렬연결로 시냅스 어레이에 사용하여 멀티-레벨을 구현하였다. 이를 Network-on-chip 형태의 가속기 내에 DAC, ADC, 버퍼 및 레지스터, shift & add 회로 등 다양한 하드웨어 블록들과 함께 구성하여 CNN 가속기에 대한 시뮬레이션을 수행하였다. 시냅스 가중치와 활성화 함수의 양자화는 16-bit으로 가정하였다. 해당 가속기 아키텍처를 위한 병렬 파이프라인을 통해 CNN 연산을 시뮬레이션한 결과, 연산효율은 약 370 GOPs/W를 달성하였으며, 양자화에 의한 정확도 열화는 3 % 이내가 되는 결과를 나타냈다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.171-175
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• 2004

A tactile stimulator array using stacked PZT is fabricated and evaluated in this paper. The purpose of this research is the development of a tactile stimulator to represent the obstacle information for the visually disabled. As a first step of this research, we investigate the physiological characteristics of tactile stimuli and design a tactile stimulator based on the investigated results. Also we evaluated a fabricated tactile stimulator. The prototype of tactile stimulator which has 2x2 tactor elements with 3mm spacing is fabricated using stacked PZT actuator. In order to evaluate the characteristics of this tactile stimulator, physiological experiments are carried out. In the experiment, the threshold of tactile stimulus intensity within a frequency range of 5-500Hz and at various stimulus amplitudes are investigated. According to the obtained experimental result, the input signal of tactile stimulator for the transfer of obstacle information is determined. Also physiological experiments of multi-stimuli recognition such as shift and rotation are carried out.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.260-264
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• 2017

Process variation effect on arch-structured gate stacked array (GSTAR) 3-D NAND flash is investigated. In case of arch-structured GSTAR, a shape of the arch channel is depending on an alignment of photo-lithography. Channel width fluctuates according to the channel hole alignment. When a shape of channel exceeds semicircle, channel width becomes longer, increasing drain current. However, electric field concentration on tunnel oxide decreases because less electric flux converges into a larger surface of tunnel oxide. Therefore, program efficiency is dependent on the process variation. Meanwhile, a radius of channel holes near the bottom side become smaller due to an etch slope. It also affects program efficiency as well as channel width. Larger hole radius has an advantage of higher drain current, but causes degradation of program speed.

• 마이크로전자및패키징학회지
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• 제27권1호
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• pp.17-24
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• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• Applied Microscopy
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• 제45권4호
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• pp.225-229
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• 2015

Transition metal dichalcogenides (TMDs) are a class of two-dimensional (2D) materials that have attracted growing interest because of their promising applications. The properties of TMDs strongly depend on the crystalline structure and the number and stacking sequence of layers in their crystals and thin films. Though electrical, mechanical, and magnetic studies of 2D materials are being conducted, there is an evident lack of direct atom-by-atom visualization, limiting insight on these highly exciting material systems. Herein, we present our recent studies on the characterization of 2D layered materials by means of aberration corrected scanning transmission electron microscopy (STEM), in particular via high angle annular dark field (HAADF) imaging. We have identified the atomic arrangements and defects in 2H stacked TMDs, 1T stacked TMDs, distorted 1T stacked TMDs, and vertically integrated heterojunctions of 2D TMDs crystals.

• Journal of information and communication convergence engineering
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• 제14권1호
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• pp.40-44
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• 2016

The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T_ILD and dielectric constant ε_r of the inter-layer distance (ILD), the doping concentration N_d (N_a), and length L_g of the channel, and the side-wall length L_SW where the stacked FETs are coupled are studied. When N_d (N_a) < 10¹⁶ cm^-3 and L_SW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d (N_a) > 10¹⁶ cm^-3 or L_SW > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or ε_r do not meet the above conditions, the interaction must be taken into consideration.