• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.7 s.349
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• pp.115-121
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• 2006

The efficiency of the multiplier largely depends on the representation of finite filed elements such as normal basis, polynomial basis, dual basis, and redundant representation, and so on. In particular, the redundant representation is attractive since it can simply implement squaring and modular reduction. In this paper, we propose an efficient bit-parallel multiplier for GF(2m) defined by an irreducible all-one polynomial using a redundant representation. We modify the well-known multiplication method which was proposed by Karatsuba to improve the efficiency of the proposed bit-parallel multiplier. As a result, the proposed multiplier has a lower space complexity compared to the previously known multipliers using all-one polynomials. On the other hand, its time complexity is similar to the previously proposed ones.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.101-106
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• 2014

This paper presents a wide dynamic range radio-frequency (RF) root-mean-square (RMS) power detector using an automatic gain control (AGC) loop. The AGC loop consists of a variable gain amplifier (VGA), RMS conversion block and gain control block. The VGA exploits dB-linear gain characteristic of the cascade VGA. The proposed circuit utilizes full-wave squaring and generates a DC voltage proportional to the RMS of an input RF signal. The proposed RMS power detector operates from 500MHz to 5GHz. The detecting input signal range is from 0 dBm to -70 dBm or more with a conversion gain of -4.53 mV/dBm. The proposed RMS power detector is designed in a 65-nm 1.2-V CMOS process, and dissipates a power of 5 mW. The total active area is $0.0097mm^2$.

• Journal of Navigation and Port Research
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• v.40 no.3
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• pp.139-146
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• 2016

Due to the continuous increasement of the container cargoes, each container port market has been growing as well. Moreover, the competition among container terminal operators located in the same port is also growing in order to attract more container cargoes. This paper looked into the market structures, market conducts and market performances of container ports in Busan and Shanghai. The index which has been most widely used to measure market structure, the Hirschman-Herfindahl Index (HHI), is computed by squaring each supplier's market share, then adding the squared shares. This paper estimated the market performance as profitability (PCM, ROA), growth (total TEU, rate of the increasement of TEU) and examined the effects of the HHI on the profitability and growth in a container terminal operators in Korea and China. The major findings of this study is that the market structure has effects on market performance in Busan port (total TEU) and Shanghai port (PCM, ROA and total TEU). As a result of analysing this study, market structure has an effect on market performance in Busan and Shanghai port, but the power of influence can be changed by market concentration index and various market conduct of companies.

• Current Research on Agriculture and Life Sciences
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• v.32 no.4
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• pp.185-188
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• 2014

The movement, survival, and weight gain of Helicoverpa armigera $H{\ddot{u}}bner$ (Lepidoptera: Noctuidae) first instar larvae were studied on CB9, CB10 and SR05 cotton varieties under field conditions. The neonate H. armigera were released on the cotton varieties at the squaring stage of the plants and, after a period of 72 hours, the survival, weight gain, and final location of the larvae were observed. While the different cotton varieties had no effect on the survival and weight gain of the larvae, the release locations on the cotton varieties had a significant influence on the larval survival and weight gain. The larvae fed small squares of the cotton varieties were significantly heavier and showed a higher mortality than the larvae fed leaflets and mature leaves. For the cotton varieties in this study, the larvae released on leaflets showed a significantly higher rate of recovery compared to the larvae released on mature leaves and squares. This study also found that that the larvae on leaflets did not move up or downward unlike the larvae on mature leaves and squares. This information on the foraging behavior of larvae on cotton varieties will assist researchers to interpret field data and thereby help with the development of pest management decisions.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.4
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• pp.17-25
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• 2008

Because Chinese Remainder Theorem based RSA (RSA CRT) offers a faster version of modular exponentiation than ordinary repeated squaring, it is promoting with standard. Unfortunately there are major security issues associated with RSA CRT, since Bellcore announced a fault-based cryptanalysis against RSA CRT in 1996. In 1997, Shamir developed a countermeasure using error free immune checking procedure. And soon it became known that the this checking procedure can not effect as the countermeasures. Recently Yen proposed two hardware fault immune protocols for RSA CRT, and this two protocols do not assume the existence of checking procedure. However, in FDTC 2006, the method of attack against the Yen's two protocols was introduced. In this paper, the main purpose is to present a countermeasure against the method of attack from FDTC 2006 for CRT-RSA. The proposed countermeasure use a characteristic bit operation and dose not consider an additional operation.

• Communications of Mathematical Education
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• v.37 no.3
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• pp.419-442
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• 2023

This study investigated fifth graders' understanding of variables from a generalized arithmetic and a functional perspectives of early algebra. Specifically, regarding a generalized perspective, we included the property of 1, the commutative property of addition, the associative property of multiplication, and a problem context with indeterminate quantities. Regarding the functional perspective, we covered additive, multiplicative, squaring, and linear relationships. A total of 246 students from 11 schools participated in this study. The results showed that most students could find specific values for variables and understood that equations involving variables could be rewritten using different symbols. However, they struggled to generalize problem situations involving indeterminate quantities to equations with variables. They also tended to think that variables used in representing the property of 1 and the commutative property of addition could only be natural numbers, and about 25% of the students thought that variables were fixed to a single number. Based on these findings, this paper suggests implications for elementary school students' understanding and teaching of variables.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.861-870
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• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1083-1091
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• 2017

This paper describes a design of cryptographic processor supporting 224-bit elliptic curves over prime field defined by NIST. Scalar point multiplication that is a core arithmetic function in elliptic curve cryptography(ECC) was implemented by adopting the modified Montgomery ladder algorithm. In order to eliminate division operations that have high computational complexity, projective coordinate was used to implement point addition and point doubling operations, which uses addition, subtraction, multiplication and squaring operations over GF(p). The final result of the scalar point multiplication is converted to affine coordinate and the inverse operation is implemented using Fermat's little theorem. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 2.7-Kbit RAM and 27,739 gate equivalents (GEs), and the estimated maximum clock frequency is 71 MHz. One scalar point multiplication takes 1,326,985 clock cycles resulting in the computation time of 18.7 msec at the maximum clock frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.7
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• pp.661-668
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• 2004

A novel method to reject the spurious signals which are occurred at Weaver-type low-IF transmitter was proposed in this paper. The spurious signals are generated by the gain and phase imbalances of I/Q channel or imperfect characteristics of 90$^{\circ}$ phase shifter in local oscillator for I/Q channel source. By deriving the gain and phase-based functions from RF spurious signal with the channel imbalance information, the lie channel imbalances were deduced as functions with magnitude and sign dependent on I/Q channel imbalance degree. The proposed method compensates the estimated I/Q channel imbalances by correlation values between the down-converted signal obtained by squaring the output signal itself using a simple mixer and the modified baseband signal. By comparing two signals after A/D conversion, the magnitude and sign of each type of imbalances can be determined separately and simultaneously. Based on the I/Q channel imbalance compensation, the spurious signals can be reduced by adjusting the gain and phase values of I or Q channel signal. The way to estimate the channel imbalances of the up-conversion mixer was presented and verified by using theoretical derivations and computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.103-112
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• 2010

In this paper, we propose a coarse and fine frequency synchronization method which is suitable for the 3GPP(3rd Generation Partnership Project) LTE(Long Term Evolution) FDD(Frequency Division Duplexing) / TDD(Time Division Duplexing) dual mode system. In general, PSS(Primary Synchronization Signal) correlation based estimation method and CP(Cyclic Prefix) correlation based tracking loop are applied for coarse and fine frequency synchronization in 3GPP LTE OFDMA(Orthogonal Frequency Division Multiple Access) system, respectively. However, the conventional coarse frequency synchronization method has performance degradation caused by fading channel and squaring loss. Also, the conventional fine frequency synchronization method cannot guarantee stable operation in TDD mode because of signal power difference between uplink and downlink subframe. Therefore, in this paper, we propose enhanced coarse and fine frequency synchronization methods which can estimate more accurately in multi-path fading channel and high speed channel environments and has stable operation for TDD frame structure, respectively. By computer simulation, we show that the proposed methods outperform the conventional methods, and verify that the proposed frequency synchronization method can guarantee stable operation in 3GPP LTE FDD/TDD dual mode downlink receiver.