• 한국재료학회지
• /
• 제12권3호
• /
• pp.211-214
• /
• 2002

Properties of 52/48 PZT films with various thicknesses for piezoelectric micro-electro mechanical systems (MEMS) devices fabricated by multi-coating method on $Pt(3500{\AA})/Ti(400{\AA})/SiO_2(3000{\AA})/Si$(525$\mu\textrm{m}$) substrates were investigated. PZT films were deposited by spin-coating process at 3500 rpm for 30 sec, followed by pyrolysis at 45$0^{\circ}C$ for 10 min producing the thickness of about 120nm. These processes were repeated 4, 8, 12, 16 and 20 times in order to have various thicknesses, respectively. Finally, they were crystallized at $650^{\circ}C$ for 30 min. All thick PZT films showed dense and homogeneous surface microstructures. Thick PZT films showed crystalline structures of random orientations with increasing thickness. Dielectric constants of thick PZT films were increased with increasing film thickness and reached 800 at 100kHz for 2.3$\mu\textrm{m}$ thick PZT film. $P_r\; and\; E_c$ of 2.3$\mu\textrm{m}$ thick PZT films were about 20$\mu$C/$\textrm{cm}^2$ and 63kV/cm. Depth profile analysis by Auger Electron Spectroscopy (AES) of 4800 $\AA$ thick PZT film showed the formation of the perovskite phase on Pt layer by Pb diffusion behavior. It was considered that Pb-Pt intermediate layer promoted PZT (111) columnar structures.

• 폴리머
• /
• 제31권6호
• /
• pp.526-531
• /
• 2007

본 논문은 플렉시블 디스플레이용 stainless steel(SS) 기판의 평탄막 재료로서 유기 및 유기/무기 하이브리드 에폭시 레진을 연구한 첫 결과를 보고한다. 유기 에폭시로는 diglycidyl ether of bisphenol A(DGEBA)를, 하이브리드 에폭시는 실세스퀴옥산이 포함된 octa(dimethylsiloxypropylglycidylether) silsesquioxane(OG)를 선택하였다. 경화제로는 diaminodiphenylmethane(DDM)을 에폭시와 1 : 2 당량비로 사용하였으며 두 물질 모두 SS 기판위에 어려움 없이 코팅이 되었다. TGA로 살펴본 열 안정성 분석은 순수한 물질이나 경화된 필름이나 모두 OG가 DGEBA 보다 안정하며 AFM에 의한 필름 표면의 관찰은 필름이 충분히 두꺼운 경우$(>\;1\;{\mu})\;1{\sim}2\;nm$ 정도의 표면 거칠기 값을 갖는 평탄한 면이 얻어진다는 것을 보여주었다. 또 이 필름들은 $0{\sim}10000$ 초에 걸치는 시간 동안 100 V와 $100^{\circ}C$의 외부 스트레스를 받은 후에도 일정한 유전 상수(${\sim}3.5$), 정전 용량 및 전류의 흐름을 나타내 절연 특성이 안정되어 있다는 것을 알 수 있었다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 제38회 하계학술대회
• /
• pp.1313-1314
• /
• 2007

This paper presents organic thin-film transistors (OTFTs) with poly(3-hexylthiophene)(P3HT) semiconductor and several polymeric dielectric materials of poly(vinyl phenol)(PVP), poly(vinyl alcohol)(PVA), and polyimide(PI) by using soluble process. The fabricated OTFT's have inverted staggered structure using transmission line method(TLM) pattern. In order to evaluate the electrical characteristics of the OTFT, capacitance-voltage(C-V) and current-voltage(I-V) were measured. C-V graphs were measured at several frequencies of 100 Hz, 1 kHz, and 1 MHz and ID-VDS graphs according to $V_{GS}$. The current on/off ratio and threshold voltage with each of PVP, PVA, and PI based OTFTs were measured to $10^3$, and -0.36, -0.41, and -0.62 V. Also, the calculated mobility with each of PVP, PVA, and PI was 0.097, 0.095, and 0.028 $cm^{2}V^{-1}s^{-1}$, respectively. In the cases of PVP and PVA, the hole mobility of P3HT was in excellent agreement with the published value of 0.1 $cm^{2}V^{-1}s^{-1}$.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.431-432
• /
• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2009년도 제38회 동계학술대회 초록집
• /
• pp.200-200
• /
• 2010

In recent times, metal oxide semiconductors thin films transistor (TFT), such as zinc and indium based oxide TFTs, have attracted considerable attention because of their several advantageous electrical and optical properties. There are many deposition methods for fabrication of ZnO-based materials such as chemical vapor deposition, RF/DC sputtering and pulsed laser deposition. However, these vacuum process require expensive equipment and result in high manufacturing costs. Also, the methods is difficult to fabricate various multicomponent oxide semiconductor. Recently, several groups report solution processed metal oxide TFTs for low cost and non vacuum process. In this study, we have newly developed solution-processed TFTs based on Ti-related multi-component transparent oxide, i. e., InTiO as the active layer. We propose new multicomponent oxide, Titanium indium oxide(TiInO), to fabricate the high performance TFT through the sol-gel method. We investigated the influence of relative compositions of Ti on the electrical properties. Indium nitrate hydrate [$In(NO^3).xH_2O$] and Titanium isobutoxide [$C_{16}H_{36}O_4Ti$] were dissolved in acetylacetone. Then monoethanolamine (MEA) and acetic acid ($CH_3COOH$) were added to the solution. The molar concentration of indium was kept as 0.1 mol concentration and the amount of Ti was varied according to weighting percent (0, 5, 10%). The complex solutions become clear and homogeneous after stirring for 24 hours. Heavily boron (p+) doped Si wafer with 100nm thermally grown $SiO_2$ serve as the gate and gate dielectric of the TFT, respectively. TiInO thin films were deposited using the sol-gel solution by the spin-coating method. After coating, the films annealed in a tube furnace at $500^{\circ}C$ for 1hour under oxygen ambient. The 5% Ti-doped InO TFT had a field-effect mobility $1.15cm^2/V{\cdot}S$, a threshold voltage of 4.73 V, an on/off current ratio grater than $10^7$, and a subthreshold slop of 0.49 V/dec. The 10% Ti-doped InO TFT had a field-effect mobility $1.03\;cm^2/V{\cdot}S$, a threshold voltage of 1.87 V, an on/off current ration grater than $10^7$, and a subthreshold slop of 0.67 V/dec.

• Bulletin of the Korean Chemical Society
• /
• 제32권1호
• /
• pp.263-272
• /
• 2011

Highly luminescent and monodisperse InP quantum dots (QDs) were prepared by a non-organometallic approach in a non-coordinating solvent. Fatty acids with well-defined chain lengths as the ligand, a non coordinating solvent, and a thorough degassing process are all important factors for the formation of high quality InP QDs. By varying the molar concentration of indium to ligand, QDs of different size were prepared and their absorption and emission behaviors studied. By spin-coating a colloidal solution of InP QD onto a silicon wafer, InP QD thin films were obtained. The thickness of the thin films cured at 60 and $200^{\circ}C$ were nearly identical (approximately 860 nm), whereas at $300^{\circ}C$, the thickness of the thin film was found to be 760 nm. Different contrast regions (A, B, C) were observed in the TEM images, which were found to be unreacted precursors, InP QDs, and indium-rich phases, respectively, through EDX analysis. The optical properties of the thin films were measured at three different curing temperatures (60, 200, $300^{\circ}C$), which showed a blue shift with an increase in temperature. It was proposed that this blue shift may be due to a decrease in the core diameter of the InP QD by oxidation, as confirmed by the XPS studies. Oxidation also passivates the QD surface by reducing the amount of P dangling bonds, thereby increasing luminescence intensity. The dielectric properties of the thin films were also investigated by capacitance-voltage (C-V) measurements in a metal-insulator-semiconductor (MIS) device. At 60 and $300^{\circ}C$, negative flat band shifts (${\Delta}V_{fb}$) were observed, which were explained by the presence of P dangling bonds on the InP QD surface. At $300^{\circ}C$, clockwise hysteresis was observed due to trapping and detrapping of positive charges on the thin film, which was explained by proposing the existence of deep energy levels due to the indium-rich phases.

• 한국전기전자재료학회논문지
• /
• 제17권1호
• /
• pp.7-15
• /
• 2004

The ferroelectric SBT thin films as a material of capacitors for non-volatile FRAMs have some problems that its remanent polarization value is relatively low and the crystallization temperature is quite high abovc 80$0^{\circ}C$. Therefore, in this paper, SBTN solution with S $r_{0.9}$B $i_{2.1}$T $a_{1.8}$N $b_{0.2}$$O_{9}$ composition was synthesized by sol-gel method. Sr(O $C_2$ $H_{5}$)$_2$, Bi(TMHD)$_3$, Ta(O $C_2$ $H_{5}$)$_{5}$and Nb(O $C_2$ $H_{5}$)$_{5}$ were used as precursors, which were dissolved in 2-methoxyethanol. SBTN thin films with 200 nm thickness were deposited on Pt/Ti $O_2$/ $SiO_2$/Si substrates by spin-coating. UV-irradiation in a power of 200 W for 10 min and rapid thermal annealing in a 5-Torr-oxygen ambient at 76$0^{\circ}C$ for 60 sec were used to promote crystallization. The films were well crystallized and fine-grained after annealing at $650^{\circ}C$ in oxygen ambient. The electrical characteristics of 2Pr=11.94 $\mu$C/$\textrm{cm}^2$, Ps＋/Pr＋=0.54 at the applied voltage of 5 V were obtained for a 200-nm-thick SBTN films. This results show that 2Pr values of the UV irradiated and rapid thermal annealed SBTN thin films at the applied voltage of 5 V were about 57% higher than those of no additional processed SBTN thin films. thin films.lms.s.s.