• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.258-261
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• 2009

In this work we present a process to fabricate lowtemperature polysilicon (LTPS) TFTs on polyimide (PI) layers, spin-coated on Si-wafer used as rigid carrier. This process has been then used to fabricate elementary circuits as well as circuits for sensor applications.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1754-1756
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• 2000

Organic semiconductors based on fused-ring polycyclic aromatic hydrocarbon have great potential to be utilized as an active layer for electronic and optoelectronic devices. In this study, pentacene thin films and electrode materials were deposited by Organic Molecular Beam Deposition(OMBD) and vacuum evaporation respectively. For the gate dielectric, polyamic acid was spin-coated and cured into polyimide at 350$^{\circ}C$. Electrical characteristics of the devices were investigated, where the channel length and width was 50${\mu}m$ and 5mm. It was found that field effect mobility was 0.012$cm^{2}/Vs$, and on/off current ratio was $10^5$.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.271-274
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• 2011

Screen-printed source and drain electrodes were used for a spin-coated and inkjet-processed zinc-tin oxide (ZTO) TFTs for the first time. Source and drain were silver nanoparticles. Channel length was patterned using screen printing technology. Different silver nanoinks and process parameters were tested to find optimal source and drain contacts Relatively good electrical properties of a screen-printed inkjet-processed oxide TFT were obtained as follows; a mobility of 1.20 $cm^2$/Vs, an on-off current ratio of $10^6$, a Vth of 5.4 V and a subthreshold swing of 1.5 V/dec.

• Korean Journal of Materials Research
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• v.21 no.2
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• pp.115-119
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• 2011

Si Nanowire (NW) field effect transistors (FETs) were fabricated on hard Si and flexible polyimide (PI) substrates, and their electrical characteristics were compared. Si NWs used as channels were synthesized by electroless etching method at low temperature, and these NWs were refined using a centrifugation method to get the NWs to have an optimal diameter and length for FETs. The gate insulator was poly(4-vinylphenol) (PVP), prepared using a spin-coating method on the PI substrate. Gold was used as electrodes whose gap was 8 ${\mu}m$. These gold electrodes were deposited using a thermal evaporator. Current-voltage (I-V) characteristics of the device were measured using a semiconductor analyzer, HP-4145B. The electrical properties of the device were characterized through hole mobility, $I_{on}/I_{off}$ ratio and threshold voltage. The results showed that the electrical properties of the TFTs on PVP were similar to those of TFTs on $SiO_2$. The bending durability of SiNWs TFTs on PI substrate was also studied with increasing bending times. The results showed that the electrical properties were maintained until the sample was folded about 500 times. But, after more than 1000 bending tests, drain current showed a rapid decrease due to the defects caused by the roughness of the surface of the Si NWs and mismatches of the Si NWs with electrodes.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Bulletin of the Korean Chemical Society
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• v.35 no.2
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• pp.494-500
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• 2014

Indium-doped zinc oxide nanocrystals (IZO NCs), capped with stearic acid (SA) of different sizes, were synthesized using a hot injection method in a noncoordinating solvent 1-octadecene (ODE). The ligand exchange process was employed to modify the surface of IZO NCs by replacing the longer-chain ligand of stearic acid with the shorter-chain ligand of butylamine (BA). It should be noted that the ligand-exchange percentage was observed to be 75%. The change of particle size, morphology, and crystal structures were obtained using a field emission scanning electron microscope (FE-SEM) and X-ray diffraction pattern results. In our study, the 5 nm and 10 nm IZO NCs capped with stearic acid (SA-IZO) were ligand-exchanged with butylamine (BA), and were then spin-coated on a thermal oxide ($SiO_2$) gate insulator to fabricate a thin film transistor (TFT) device. The films were then annealed at various temperatures: $350^{\circ}C$, $400^{\circ}C$, $500^{\circ}C$, and $600^{\circ}C$. All samples showed semiconducting behavior and exhibited n-channel TFT. Curing temperature dependent on mobility was observed. Interestingly, mobility decreases with the increasing size of NCs from 5 to 10 nm. Miller-Abrahams hopping formalism was employed to explain the hopping mechanism insight our IZO NC films. By focusing on the effect of size, different curing temperatures, electron coupling, tunneling rate, and inter-NC separation, we found that the decrease in electron mobility for larger NCs was due to smaller electronic coupling.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.658-658
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• 2013

Graphene is an attractive material for various device applications due to great electrical properties and chemical properties. However, lack of band gap is significant hurdle of graphene for future electrical device applications. In the past few years, several methods have been attempted to open and tune a band gap of graphene. For example, researchers try to fabricate graphene nanoribbon (GNR) using various templates or unzip the carbon nanotubes itself. However, these methods generate small driving currents or transconductances because of the large amount of scattering source at edge of GNRs. At 2009, Bai et al. introduced graphene nanomesh (GNM) structures which can open the band gap of large area graphene at room temperature with high current. However, this method is complex and only small area is possible. For practical applications, it needs more simple and large scale process. Herein, we introduce a photosensitive graphene device fabrication using CdSe QD coated nano-porous graphene (NPG). In our experiment, NPG was fabricated by thin film anodic aluminum oxide (AAO) film as an etching mask. First of all, we transfer the AAO on the graphene. And then, we etch the graphene using O2 reactive ion etching (RIE). Finally, we fabricate graphene device thorough photolithography process. We can control the length of NPG neckwidth from AAO pore widening time and RIE etching time. And we can increase size of NPG as large as 2 $cm^2$. Thin CdSe QD layer was deposited by spin coatingprocess. We carried out NPG structure by using field emission scanning electron microscopy (FE-SEM). And device measurements were done by Keithley 4200 SCS with 532 nm laser beam (5 mW) irradiation.

• Journal of Industrial and Engineering Chemistry
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• v.68
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• pp.399-405
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• 2018

We report the fabrication of organic field-effect transistors (OFETs) via spray coating of electrochemically exfoliated graphene (EEG) and conducting polymer hybrid as electrodes. To reduce the roughness and sheet resistance of the EEG electrodes, subsequent coating of conducting polymer (poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS)) and acid treatment was performed. After that, active channel layer was developed by spin coating of semiconducting poly(3-hexylthiophene) on the hybrid electrodes to define the bottom gate bottom contact configuration. The OFET devices with the EEG/PEDOT:PSS hybrid electrodes showed a reasonable electrical performances (field effect mobility = $0.15cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^2$, and threshold voltage = -1.57V). Furthermore, the flexible OFET devices based on the Polydimethlsiloxane (PDMS) substrate and ion gel dielectric layer exhibited higher electrical performances (field effect mobility = $6.32cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^3$, and threshold voltage = -1.06V) and excellent electrical stability until 1000 cycles of bending test, which means that the hybrid electrode is applicable to various organic electronic devices, such as flexible OFETs, supercapacitors, organic sensors, and actuators.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.37-37
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• 2010

Silicate-silsesquioxane or siloxane-silsesquioxane hybrid thin films are strong candidates as matrix materials for ultra low dielectric constant (low-k) thin films. We synthesized the silicate-silsesquioxane hybrid resins from tetraethoxyorthosilicate (TEOS) and methyltrimethoxysilane (MTMS) through hydrolysis and condensation polymerization by changing their molar ratios ([TEOS]:[MTMS] = 7:3, 5:5, and 3:7), spin-coating on Si(100) wafers. In the case of [TEOS]:[MTMS] 7:3, the dielectric permittivity value of the resultant thin film was measured at 4.30, exceeding that of the thermal oxide (3.9). This high value was thought to be due to Si-OH groups inside the film and more extensive studies were performed in terms of electronic, ionic, and orientational polarizations using Debye equation. The relationship between the mechanical properties and the synthetic conditions of the silicate-silsesquioxane precursors was also investigated. The synthetic conditions of the low-k films have to be chosen to meet both the low orientational polarization and high mechanical properties requirements. In addition, we have investigated a new solution-based approach to the synthesis of semiconducting chalcogenide films for use in thin-film transistor (TFT) devices, in an attempt to develop a simple and robust solution process for the synthesis of inorganic semiconductors. Our material design strategy is to use a sol-gel reaction to carry out the deposition of a spin-coated CdS film, which can then be converted to a xerogel material. These devices were found to exhibit n-channel TFT characteristics with an excellent field-effect mobility (a saturation mobility of ${\sim}\;48\;cm^2V^{-1}s^{-1}$) and low voltage operation (< 5 V). These results show that these semiconducting thin film materials can be used in low-cost and high-performance printable electronics.