• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권1호
• /
• pp.88-98
• /
• 2012

In this paper, the relationship between the bandwidth (BW) and power efficiency of a source follower based (SFB) filter is quantitatively analyzed, and a design methodology for a SFB filter for optimized BW - power consumption is introduced. The proposed design methodology achieves a maximum BW at a target quality (Q) factor for the given power consumption constraint by controlling design factors individually. In order to achieve the target BW from the maximized BW, a tuning method is introduced. Through the proposed design methodology, a fourth order Butterworth filter was implemented in 0.18 ${\mu}m$ CMOS technology. The measured BW, power consumption, and IIP3 are 100 MHz, 33 ${\mu}W$, and 9 dBm, respectively. Compared with other filter structures, the measured results show high BW - power efficiency.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
• /
• pp.1243-1246
• /
• 2006

A new source follower circuit for the integrated circuit of AMLCDs is proposed. Active load is added and calibration operation is applied to compensate the circuits. Proposed circuit is capable of minimizing the variation from both timing and device variations through measured results, the uniformity and bias effect are discussed.

• 센서학회지
• /
• 제19권1호
• /
• pp.25-30
• /
• 2010

This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a $0.5{\mu}m$ CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.

• ETRI Journal
• /
• 제38권2호
• /
• pp.235-243
• /
• 2016

A low-noise readout integrated circuit (ROIC) for a microelectromechanical systems (MEMS) microphone is presented in this paper. A positive feedback signal amplification technique is applied at the front-end of the ROIC to minimize the effect of the output buffer noise. A feedback scheme in the source follower prevents degradation of the noise performance caused by both the noise of the input reference current and the noise of the power supply. A voltage booster adopts noise filters to cut out the noise of the sensor bias voltage. The prototype ROIC achieves an input referred noise (A-weighted) of -114.2 dBV over an audio bandwidth of 20 Hz to 20 kHz with a $136{\mu}A$ current consumption. The chip is occupied with an active area of $0.35mm^2$ and a chip area of $0.54mm^2$.

• 센서학회지
• /
• 제26권4호
• /
• pp.223-227
• /
• 2017

Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sensitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during integration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sensitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator determines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A $94{\times}150$ pixel array image sensor was designed using a conventional $0.18{\mu}m$ CMOS process and its performance was simulated.

• 대한전자공학회논문지
• /
• 제25권4호
• /
• pp.417-421
• /
• 1988

In order to analyze the blooming suppression mechanism of a MOS image sensor, test photodiodes have been fabricated and characterized by attaching a source follower circuit. The blooming suppression ability of npn structure compared to that of np structure is quantitatively analyzed and measured by experiment. The dependency of the blooming current on the substrate voltage, the vertical MOS gate voltage and the video voltage is measured and the optimum condition for blooming suppression is presented.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 하계종합학술대회 논문집
• /
• pp.247-250
• /
• 1999

This paper presents characteristics of neuron-MOSFET for the implementation of logic circuits such at the inverter and D/A converter. Neuron-MOSFETS were fabricated using double poly CMOS process. From the measured results, it was found that noise margin of the inverter was dependant on the coupling ratio and a complete D/A characteristics of the source follower could be obtained by using any input Sate as a control gate.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
• /
• pp.61-64
• /
• 2000

This paper describes a RF Down-Conversion Mixer for mobile communication systems. This circuit achieves low voltage operation and low power consumption by reducing stacked devices of conventional gilbert cell mixer. In order to reduce stacked devices, we use source-follower structure. The proposed RF Down-Conversion mixer operates up to 1.85GHz at 1.5V power supply with 0.25um CMOS technology and consumes 2.2mA.

• 한국산학기술학회논문지
• /
• 제11권4호
• /
• pp.1222-1228
• /
• 2010

고속 PMIC를 위한 빠른 천이 응답 시간을 가지는 CMOS LDO 레귤레이터를 설계하였다. 제안하는 LDO 레귤레이터 회로는 기준전압회로와 오류증폭회로, 파워 트랜지스터 등으로 이루어지며, 출력전압의 안정성을 높이기 위하여 오류증폭 회로와 파워 트랜지스터 사이에 버퍼로써 2단 광대역 OTA를 추가하였다. 기존의 연구에서 제안된 가장 간단하게 구현할 수 있는 버퍼로는 소스팔로워 구조가 있으나, 출력 스윙이 좁고 신호 대 잡음비가 저하되는 문제점이 있었다. 본 논문에서는 2단 광대역 OTA를 버퍼로 사용하여 LDO 전압 레귤레이터의 출력 특성을 개선하였다. $0.5{\mu}m$ CMOS 공정을 이용하여 모의실험 한 결과, 라인 레귤레이션은 16 mV/V, 부하 레귤레이션 0.007 %/mA를 얻었다.

• 센서학회지
• /
• 제15권5호
• /
• pp.341-346
• /
• 2006

We have fabricated SOI CMOS active pixel image sensor with the pinned photodiode on handle wafer in order to reduce dark currents and improve spectral response. The structure of the active pixel image sensor is 4 transistors APS which consists of a reset and source follower transistor on seed wafer, and is comprised of the photodiode, transfer gate, and floating diffusion on handle wafer. The source of dark current caused by the interface traps located on the surface of a photodiode is able to be eliminated, as we apply the pinned photodiode. The source of dark currents between shallow trench isolation and the depletion region of a photodiode can be also eliminated by the planner process of the hybrid bulk/SOI structure. The photodiode could be optimized for better spectral response because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. The dark current was about 6 pA at 3.3 V of floating diffusion voltage in the case of transfer gate TX = 0 V and TX=3.3 V, respectively. The spectral response of the pinned photodiode was observed flat in the wavelength range from green to red.