• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.102-106
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• 2003

This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.459-462
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• 2005

Recently, the PDP is the most remarkable media for a next generation display device. But the PDP is a high power consumption device. It is to required a high efficiency power supply. We reported the experimental result the high efficiency PDP power supply for 550w class. The proposed converter is quasi-resonant flyback topology, it achieves soft-switching in the single-switch flyback converter. As a result, we realize to very high efficiency power supply for PDP of 95% at 400v dc input and 550Watt output.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.16-23
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• 1983

A programmable controller (PC) which can control general sequential process is developed. The Z-8OA microprocessor-based PC includes hardwares such as programming device, input/output modules, timer/counter modules, and power-failure recovery module which for soft-ware, initialization program, monitor program, execution program, and power-failure recovery program are developed. In particular, the PC is designed in such a way that a timer can be used several times in different time intervals and a skip capability is incorporated in the user program to reduce scan time.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.4
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• pp.117-125
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• 2014

In this paper, a novel hardware architecture of the LT codec is presented where non-BP based decoding algorithm is applied. Novel LT codec architecture is designed with an efficient degree distribution unit using Verilog HDL. To perform permutation operation, different initial valued or time shifted counters have been used to get pretty well permutations and an effect of randomness. The codec will take 128 bits as input and produce 256 encoded output bits. The simulation results show expected performances as the implemented distribution and the original distribution are pretty same. The proposed LT codec takes 257.5 cycle counts and $2.575{\mu}s$ for encoding and decoding instead of 5,204,861 minimum cycle counts and 4.43s of the design mentioned in the previous works where iterative soft BP decoding was used in ASIC and ASIP implementation of the LT codec.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2021.06a
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• pp.105-108
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• 2021

Generative adversarial networks (GANs) have reached a great result at creating the synthesis image, especially in the face generation task. Unlike other deep learning tasks, the input of GANs is usually the random vector sampled by a probability distribution, which leads to unstable training and unpredictable output. One way to solve those problems is to employ the label condition in both the generator and discriminator. CelebA and FFHQ are the two most famous datasets for face image generation. While CelebA contains attribute annotations for more than 200,000 images, FFHQ does not have attribute annotations. Thus, in this work, we introduce a method to learn the attributes from CelebA then predict both soft and hard labels for FFHQ. The evaluated result from our model achieves 0.7611 points of the metric is the area under the receiver operating characteristic curve.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.4
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• pp.380-387
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• 2005

We report the performance of an open-frame type low-voltage high-current DC-DC converter module developed using an active clamp forward converter circuit and single ended rectifier. The converter module is designed with the specifications of an 3.3V output voltage, 30A output current, 100W output power and 36-75V input voltage. The synchronous rectifier is used to reduce the conduction loss at high current level and constant current control using precision PCB resistance is adapted to enhance the over current protection function in the system configuration. A prototype converter module is successfully implemented within 8mm height and quarter brick size (58x37mm) and recorded an $95W/in^3$ power density, 90.6$\%$ efficiency and 0.07$\%$ voltage regulation for the entire Input voltage range, thereby demonstrating its application potentials to future telecommunication electronics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.255-266
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• 2015

In this paper, a low-complexity and low-power soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multi-stage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clock-gating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately $0.31mm^2$ with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.

• Earthquakes and Structures
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• v.6 no.2
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• pp.201-216
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• 2014

Many building codes use the empirical equation to determine fundamental period of vibration where in effect of length, width and the stiffness of the building is not explicitly accounted for. Also the equation, estimates the fundamental period of vibration with large safety margin beyond certain height of the building. An attempt is made to arrive at the simple empirical equations for fundamental period of vibration with adequate safety margin, using soft computing technique of Genetic Programming (GP). In the present study, GP models are developed in four categories, varying the number of input parameters in each category. Input parameters are chosen to represent mass, stiffness and geometry of the buildings directly or indirectly. Total numbers of 206 buildings are analyzed out of which, data set of 142 buildings is used to develop these models. It is observed that GP models developed under B and C category yield the same equation for fundamental period of vibration along X direction as well as along Y direction whereas the equation of fundamental period of vibration along X direction and along Y direction is of the same form for category D. The equations obtained as an output of GP models clearly indicate the influence of mass, geometry and stiffness of the building over fundamental period of vibration. These equations are then compared with the equation recommended by other researcher.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.6
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• pp.363-372
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• 2015

Recent some SoC FPGA Releases that integrate ARM processor and FPGA fabric show better performance compared to the ASIC SoC used in typical embedded image processing system. In this study, using the above advantages, we implement a SoC FPGA-based Real-Time Object Recognition and Tracking System. In our system, the video input and output, image preprocessing process, and background subtraction processing were implemented in FPGA logics. And the object recognition and tracking processes were implemented in ARM processor-based programs. Our system provides the processing performance of 5.3 fps for the SVGA video input. This is about 79 times faster processing power than software approach based on the Nios II Soft-core processor, and about 4 times faster than approach based the HPS processor. Consequently, if the object recognition and tracking system takes a design structure combined with the FPGA logic and HPS processor-based processes of recent SoC FPGA Releases, then the real-time processing is possible because the processing speed is improved than the system that be handled only by the software approach.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.24-30
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• 2014

A digital RDA(Retrodirective Antenna) system is a retransmit system that received signal without prior information turn back by estimated phase of the signal to received direction. The RDA can decrease consumption of power by increase of directivity because signal concentrates on received direction compare to omni-direction antenna which transmit power all direction. Generally, the RDA is known to show better performance than the single-antenna system in multi-path environment. However, the RDA occurs performance degradation in serious ISI channel. In this paper, to solve this problem, we propose retrodirective antenna combined with turbo equalizer combined which can compensate serious ISI channel, we increase the BER performance through proposed retrodirective antenna combined with turbo equalizer in serious ISI channel.