• Journal of Communications and Networks
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• v.10 no.4
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• pp.371-383
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• 2008

Application of network coding in wireless two-way relay channels (TWRC) has received much attention recently because its ability to improve throughput significantly. In traditional designs, network coding operates at upper layers above (including) the link layer and it requires the input packets to be correctly decoded. However, this requirement may limit the performance and application of network coding due to the unavoidable fading and noise in wireless networks. In this paper, we propose a new wireless network coding scheme for TWRC, which is referred to as soft network coding (SoftNC), where the relay nodes applies symbol-by-symbol soft decisions on the received signals from the two end nodes to come up with the network coded information to be forwarded. We do not assume further channel coding on top of SoftNC at the relay node (channel coding is assumed at the end nodes). According to measures of the soft information adopted, two kinds of SoftNC are proposed: amplify-and-forward SoftNC (AF-SoftNC) and soft-bit-forward SoftNC (SBF-SoftNC). We analyze the both the ergodic capacity and the outage capacity of the two SoftNC schemes. Specifically, analytical form approximations of the ergodic capacity and the outage capacity of the two schemes are given and validated. Numerical simulation shows that our SoftNC schemes can outperform the traditional network coding based two-way relay protocol, where channel decoding and re-encoding are used at the relay node. Notable is the fact that performance improvement is achieved using only simple symbol-level operations at the relay node.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.10
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• pp.841-849
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• 2012

This paper proposes an low-complexity soft-output multiple-input multiple-output (soft-MIMO) detection algorithm for achieving soft-output maximum-likelihood (soft-ML) performance under max-log approximation. The proposed algorithm is based on a parallel tree-search (PTS) applying a channel ordering by a sorted-QR decomposition (SQRD) with altered sort order. The empty-set problem that can occur in calculation of log-likelihood ratio (LLR) for each bit is solved by inserting additional nodes at each search level. Since only the closest node is inserted among nodes with opposite bit value to a selected node, the proposed node insertion scheme is very efficient in the perspective of computational complexity. The computational complexity of the proposed algorithm is approximately 37-74% of that of existing algorithms, and from simulation results for a $4{\times}4$ system, the proposed algorithm shows a performance degradation of less than 0.1dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1747-1750
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• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.948-953
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• 2010

In this paper, we propose multi-bit soft error detection method which can use an instruction cache of superscalar CPU architecture. Proposed method is applied to high-speed static RAM for instruction cache. Using 1D parity and interleaving, it has less memory overhead and detects more multi-bit errors comparing with other methods. It only detects occurrence of soft errors in static RAM. Error correction is treated like a cache miss situation. When soft errors are occurred, it is detected by 1D parity. Instruction cache just fetch the words from lower-level memory to correct errors. This method can detect multi-bit errors in maximum 4$\times$4 window.

• Journal of the Korean Operations Research and Management Science Society
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• v.31 no.3
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• pp.1-10
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• 2006

In this paper we deal with a cell planning issue arisen in a CDMA based multicast network. In a CDMA based wireless network, a terminal can significantly reduce the bit error rate via the cohesion of data streams from multiple base stations. In this case, multiple base stations have to be operated according to a common time line. The cells whose base stations are operated as such are called soft-combined cells. Therefore, a terminal can take advantage of error rate reduction, if the terminal is in a soft-combined cell and at least one neighboring cell is also soft-combined. However, as soft-combining operation gives heavy burden to the network controller, the limited number of cells can be soft-combined. Our problem us to find a limited number of soft-combined cells such that the benefit of the soft-combining operation is maximized.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.117-120
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• 2005

The SONOS devices have been fabricated by the conventional $0.35{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with NOR array. Two-bit operation using conventional process achieve the high density memory compare with other two-bit memory. Lateral diffusion phenomenon in the two-bit operation cause soft error in the memory. In this study, the programming conditions arc investigated in order to reduce lateral diffusion for two-bit operation of CSL-NOR type SONOS flash cell.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.4
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• pp.1296-1309
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• 2023

In this paper, based on the soft cancellation (SCAN) bit-flipping (SCAN-BF) algorithm, a generalized SCAN bit-flipping (GSCAN-BF-Ω) decoding algorithm is carried out, where Ω represents the number of bits flipped or corrected at the same time. GSCAN-BF-Ω algorithm corrects the prior information of the code bits and flips the prior information of the unreliable information bits simultaneously to improve the block error rate (BLER) performance. Then, a joint threshold scheme for the GSCAN-BF-2 decoding algorithm is proposed to reduce the average decoding complexity by considering both the bit channel quality and the reliability of the coded bits. Simulation results show that the GSCAN-BF-Ω decoding algorithm reduces the average decoding latency while getting performance gains compared to the common multiple SCAN bit-flipping decoding algorithm. And the GSCAN-BF-2 decoding algorithm with the joint threshold reduces the average decoding latency further by approximately 50% with only a slight performance loss compared to the GSCAN-BF-2 decoding algorithm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.15-21
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• 2014

Due to the development of manufacturing technology scaling, more transistors can be placed on a cache memories of a processor. However, processors become more vulnerable to the soft errors because of highly integrated transistors, the reliability of cache memory must consider seriously at the design level. Various researches are proposed to overcome the vulnerability of soft error, but researches of tag bit are proposed very rarely. In this paper, we revaluate the reliability improvement technique for tag bit, and analyse the protection rate of write-back operation, which is a typical case of not satisfying temporal locality. We also propose the methodology to improve the protection rate of write-back operation. The experiments of the proposed scheme shows up to 76.8% protection rate without performance degradations.

• Proceedings of the Korean Magnestics Society Conference
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• 2002.12a
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• pp.180-181
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• 2002

수직기록매체에서 기록 밀도가 증가하기 위해서는 bit의 크기를 줄여야 하고, 이를 위해서는 writing head의 width와 thickness를 줄여야 한다. 그러나 head의 크기가 줄어들면 기록층의 자화를 반전시키기에 충분한 write field를 얻지 못한다. 이를 극복하기 위해 head의 tip부분을 trimming을 하여 작은 pole tip 크기를 가지면서도 큰 write field를 얻고, 여분의 magnetic field를 얻기 위해 soft underlayer를 도입하는 이중층 수직기록 매체가 제안되고 있다. (중략)

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.211-214
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• 1998

TCM(Trellis-Coded Modulation)은 대역폭과 전력이 제한된 채널환경에서 채널부호화 기술과 변조기술을 결합시켜 대역폭의 증가없이 에러정정능력을 개선시키는 통신 기술이다. 본 논문에서는 TCM 신호의 복호시 사용되는 Viterbi decoder에서 traceback depth의 감소에 따른 BER(Bit Error Rate)의 증가를 개선하기 위해 수신부에서 설정하는 traceback depth를 주기로 blocking하여 TCM encoder의 입력시퀀스에 zero padding bits를 추가시키는 새로운 알고리듬을 제안한다. 모의실험결과, traceback depth가 50인 hard decision의 경우 약 2~2.5dB, 4-level soft decision과 8-level soft decision의 경우 약 0.3~2dB의 coding gain을 얻을 수 있었다.