• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.207-210
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• 2002

This paper describes a design of multiple-mode single-output DC/DC converter which can be used in both up and down conversion. Proposed up/down converter does not produce a negative voltage which is generated in conventional buck-boost type converter. Three types of operation mode(up/down/bypass) are controlled by the input voltage sense and command signals of target output voltage. PFM(pulse frequency modulation) control is adopted and modified for fast tracking and for precise output voltage level with an aid of output voltage sense. Designed DC/DC converter has the performance of less than 5 % ripple and higher than 80 % efficiency. Chip area is 3.50 mm ${\times}$ 2.05 mm with standard 0.35 $\mu\textrm{m}$ CMOS technology.

• 전자공학회논문지A
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• 제31A권9호
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• pp.139-145
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• 1994

InGaAsP/InP PBH-DFB-LD emitting at 1.55${\mu}$m wavelength has been fabricated for 2.5Gbps optical fiber communcations. For fabrication of PBH-DFB-LD, Interference expose for grating formation 3-step LPE epitaxial growth were used. Fabricated PBH-DFB-LD operates in single longitudinal mode with larger than 35dB SMSR and wider than 3dB bandwidth of 3GHz. A 8${\mu}$m mesa structure was introduced by channel etching to reuce parasitic capacitance. To reduce pad capacitance, we designed a small electrode. 0.27mW/mA in the case of spectrum shows single logitudinal mode operation with larger thatn 30dB SMSR measured at 5mW.

• 전기전자학회논문지
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• 제22권2호
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• pp.233-241
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• 2018

블록암호 알고리듬 ARIA, AES를 기반으로 GCM (Galois/Counter Mode) 인증암호를 지원하는 암호 프로세서를 경량화 구현하였다. 설계된 암호 프로세서는 블록암호를 위한 128 비트, 256 비트의 두 가지 키 길이와 5가지의 기밀성 운영모드 (ECB, CBC, OFB, CFB, CTR)도 지원한다. 알고리듬 특성을 기반으로 ARIA와 AES를 단일 하드웨어로 통합하여 구현하였으며, CTR 암호연산과 GHASH 연산의 효율적인 동시 처리를 위해 $128{\times}12$ 비트의 부분 병렬 GF (Galois field) 곱셈기를 적용하여 전체적인 성능 최적화를 이루었다. ARIA/AES-GCM 인증암호 프로세서를 FPGA로 구현하여 하드웨어 동작을 확인하였으며, 180 nm CMOS 셀 라이브러리로 합성한 결과 60,800 GE로 구현되었다. 최대 동작 주파수 95 MHz에서 키 길이에 따라 AES 블록암호는 1,105 Mbps와 810 Mbps, ARIA 블록암호는 935 Mbps와 715 Mbps, 그리고 GCM 인증암호는 138~184 Mbps의 성능을 갖는 것으로 평가되었다.

• 조명전기설비학회논문지
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• 제17권1호
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• pp.1-9
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• 2003

본 논문에서는 고역률의 단일전력단을 갖는 형광등용 전자식 안정기를 제안하고 설계ㆍ제작하였다. 저가의 새로운 형태를 갖는 고역률 단일전력단 형광등용 전자식 안정기는 부스터 컨버터와U형 고주파 공진 인버터로 구성되어진다. 그러나, 기존의 안정기와는 달리 제안된 안정기는 브리지 다이오드를 제거하고 간단한 제어회로로 구성함으로 간단한 구조를 갖는다. 부스터 컨버터는 상용전원의 정(＋), 부(－)전압에서 각각 동작하고 불연속 모드에서 동작함으로 높은 역률을 얻을 수 있다. 63.5〔W〕의 출력을 갖는 안정기를 제작하여 실험한 결과, PF 0.99, THD 15.4%, CF 1.55의 우수한 결과를 얻을 수 있었다.

• 전기학회논문지
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• 제56권6호
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• pp.1064-1070
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• 2007

This paper presents a grid-interactive current controlled voltage source inverter (CCVSI) with uniterruptible power supply (UPS), which uses an inner current control loop (polarized ramp time (PRT)) and outer feedback control loops to improve grid power quality and UPS. To reduce the complexity, cost and number of power conversions, which results in higher efficiency, a single stage CCVSI is used. The operation of this system could be divided into the power quality control (PQC) state mode and the UPS state mode. In PQC mode, the system operated to compensate the reactive power demand by nonlinear load or variation in load. In UPS mode. the system is controlled to provide a sinusoidal voltage at the rated value for the load when the gird fail. To verify the proposed system, a comprehensive evaluation with theoretical analysis, simulation and experimental results for 1KVA load capacity is presented.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.473-473
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• 2000

This paper presents the 2-bit parallel algorithmic ADC using current mode for parallel method algorithm. It is operated by parallel conversion, 2-bit at each moment, and increase bit numbers by serial connection. The circuit operates in current mode. The comparison ratio can be controlled while working under mode operation. The circuit design used 0.8 ${\mu}{\textrm}{m}$ CMOS technology which capable to convert 2-bit in 50 ns, power consumed 0.786 nW, with input current 0-50 mA from 3V single supply. From simulation testing, the conversion rate is much faster than other method.

• Journal of Power Electronics
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• 제18권6호
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• pp.1720-1728
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• 2018

This paper proposes a novel soft starting algorithm by using PWM inverter technique to control an amplitude of the motor starting current at a single-phase induction motor (SPIM). Traditional SPIM starting methods such as a Split-Phase, Capacitor-Start, Permanent-Split Capacitor (PSC), Capacitor-Start Capacitor-Run (CSCR), basically cannot control the magnitude of starting current due to the fixed system structures. Therefore, in this paper, a soft starting algorithm based on a proportional resonant (PR) control with a variable and constant frequency is proposed to reduce the inrush current and starting up time. In addition, a transition algorithm for operation modes is devised to generate a constant voltage and constant frequency (CVCF). The validity and effectiveness of the proposed soft starting method and transition algorithm are verified through experimental results.

• 상하수도학회지
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• 제22권2호
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• pp.179-182
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• 2008

The KIDEA process, occurred in single reactor, is operated by three consequential steps, i.e., aerobic, settling, and discharge while introducing wastewater into the bottom of reactor continuously. It could accomplish biological oxidation (BOD), nitrification, denitrification (T-N), phosphate removal (T-P), and solid separation (SS) through the operational mode mentioned. Especially, this system has removed the T-P by wasting certain amount of sludge at the end of aeration phase during 5~10 minutes and not returned the activated sludge into the reactor, that is, no RAS (Return Activated Sludge). All running mode and instrumentation were controlled by the PLC equipment automatically. In this study, therefore, we have evaluated T-P removal efficiency and moisture content (MC) performance under the different excess sludge wasting mode. T-P track study and MC with TS concentration were analyzed during aerobic and settling phase. It has revealed that there was no significant difference of released T-P concentration between the first case which waste the sludge at the end of aerobic phase (0.2mg/L) and the second case which waste the sludge at 40 min of settling phase (0.25mg/L). Also, dewatering duration and MC have decreased 1.7% when TS concentration was increased from 0.31% to 0.5% during aerobic condition. Hence, it has concluded the system performance was less influenced by the operation time change of PLC program.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.793-799
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• 2016

A multi-purpose sensor interface that provides dual-mode operation of fingerprint sensing and physiological signal detection is presented. The dual-mode sensing capability is achieved by utilizing inter-pixel shielding patterns as capacitive amplifier's input electrodes. A prototype readout circuit including a fingerprint panel for feasibility verification was fabricated in a $0.18{\mu}m$ CMOS process. A single-channel readout circuit was implemented and multiplexed to scan two-dimensional fingerprint pixels, where adaptive calibration capability against pixel-capacitance variations was also implemented. Feasibility of the proposed multi-purpose interface was experimentally verified keeping low-power consumption less than 1.9 mW under a 3.3 V supply.

• Journal of Power Electronics
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• 제12권6호
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.