• Journal of IKEEE
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• v.23 no.3
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• pp.917-924
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• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.300-312
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• 2014

A single-inductor multiple-output (SIMO) DC-DC converter providing buck and boost outputs with a new switching sequence is presented. In the proposed switching sequence, which does not require any additional blocks, input energy is delivered to outputs continuously by flowing current through the inductor, which leads to high conversion efficiency regardless of the balance between the buck and boost output loads. Furthermore, instead of multiple output loop compensation, only the freewheeling current feedback loop is compensated, which minimizes the number of off-chip components and nullifies the need for the equivalent series resistance (ESR) of the output capacitor for loop compensation. Therefore, power conversion efficiency and output voltage ripples can be improved and minimized, respectively. Implemented in a 0.35-${\mu}m$ CMOS, the proposed SIMO DC-DC converter achieves high conversion efficiency regardless of the load balance between the two outputs with maximum efficiency reaching up to 82% under heavy loads.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.549-556
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• 2014

This paper proposes a highly power-efficient single-inductor multiple-outputs (SIMO) DC-DC converter with a gate charge sharing method in which gate charges of output switches are shared to improve the power efficiency and to reduce the switching power loss. The proposed converter was fabricated by using a $0.18{\mu}m$ CMOS process technology with high voltage devices of 5 V. The input voltage range of the converter is from 2.8 V to 4.2 V, which is based on a single cell lithium-ion battery, and the output voltages are 1.0 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V. Using the proposed gate charge sharing method, the maximum power efficiency is measured to be 87.2% at the total output current of 450 mA. The measured power efficiency improved by 2.1% compared with that of the SIMO DC-DC converter without the proposed gate charge sharing method.

• ETRI Journal
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• v.31 no.2
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• pp.162-172
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• 2009

A linear-prediction-based blind equalization algorithm for single-input single-output (SISO) finite impulse response/infinite impulse response (FIR/IIR) channels is proposed. The new algorithm is based on second-order statistics, and it does not require channel order estimation. By oversampling the channel output, the SISO channel model is converted to a special single-input multiple-output (SIMO) model. Two forward linear predictors with consecutive prediction delays are applied to the subchannel outputs of the SIMO model. It is demonstrated that the partial parameters of the SIMO model can be estimated from the difference between the prediction errors when the length of the predictors is sufficiently large. The sufficient filter length for achieving the optimal prediction is also derived. Based on the estimated parameters, both batch and adaptive minimum-mean-square-error equalizers are developed. The performance of the proposed equalizers is evaluated by computer simulations and compared with existing algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.23-30
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• 2011

This paper presents a Single-Inductor Multiple-Output (SIMO) DC-DC Converter with a negative feedback selection circuit to improve a regulation property at light load and to generate independent multiple outputs. The conventional SIMO DC-DC converter with a fixed negative feedback circuit cannot regulate correctly at light load. The SIMO DC-DC converter with the proposed negative feedback selection circuit has been designed in 0.35um 2-poly 3-metal BCDMOS. This converter is dual output boost converter with the 1.5V input and 2.5V, 3.0V output. The power conversion efficiency varies from 59% at 10mA loads to 85% at 50mA loads.

• Journal of Communications and Networks
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• v.5 no.2
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• pp.157-166
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• 2003

This paper deals with the problem of channel identification for Single Input Multiple Output (SIMO) slow fading channels using clustering algorithms. Due to the intrinsic memory of the discrete-time model of the channel, over short observation periods, the received data vectors of the SIMO model are spread in clusters because of the AWGN noise. Each cluster is practically centered around the ideal channel output labels without noise and the noisy received vectors are distributed according to a multivariate Gaussian distribution. Starting from the Markov SIMO channel model, simultaneous maximum ikelihood estimation of the input vector and the channel coefficients reduce to one of obtaining the values of this pair that minimizes the sum of the Euclidean norms between the received and the estimated output vectors. Viterbi algorithm can be used for this purpose provided the trellis diagram of the Markov model can be labeled with the noiseless channel outputs. The problem of identification of the ideal channel outputs, which is the focus of this paper, is then equivalent to designing a Vector Quantizer (VQ) from a training set corresponding to the observed noisy channel outputs. The Linde-Buzo-Gray (LBG)-type clustering algorithms [1] could be used to obtain the noiseless channel output labels from the noisy received vectors. One problem with the use of such algorithms for blind time-varying channel identification is the codebook initialization. This paper looks at two critical issues with regards to the use of VQ for channel identification. The first has to deal with the applicability of this technique in general; we present theoretical results for the conditions under which the technique may be applicable. The second aims at overcoming the codebook initialization problem by proposing a novel approach which attempts to make the first phase of the channel estimation faster than the classical codebook initialization methods. Sample simulation results are provided confirming the effectiveness of the proposed initialization technique.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.44-50
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• 2015

This paper presents a high speed synchronous single inductor dual output boost converter using Type-III compensation for power management in smart devices. Maintaining multiple outputs from a single inductor is becoming very important because of inductor the sizes. The uses of high switching frequency, inductor and capacitor sizes are reduced. Owing to synchronous rectification this kind of converter is suitable for SoC. The phase is controlled in time sharing manner for each output. The controller used here is Type-III, which ensures quick settling time and high stability. The outputs are stable within $58{\mu}s$. The simulation results show that the proposed scheme achieves a better overall performance. The input voltage is 1.8V, switching frequency is 5MHz, and the inductor used is 600nH. The output voltages and powers are 2.6V& 3.3V and 147mW &, 230mW respectively.