• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.171-174
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• 2006

A large number of service providers in countries all over the world have established GNSS reference station networks in the last years and are using network software today to provide a correction stream to the user as a routine service. In current GNSS network processing, all the geometric related information such as ionospheric free carrier phase ambiguities from all stations and satellites, tropospheric effects, orbit errors, receiver and satellite clock errors are estimated in one centralized Kalman filter. Although this approach provides an optimal solution to the estimation problem, however, the processing time increases cubically with the number of reference stations in the network. Until now one single Personal Computer with Pentium 3.06 GHz CPU can only process data from a network consisting of no more than 50 stations in real time. In order to process data for larger networks in real time and to lower the computational load, a federated filter approach can be considered. The main benefit of this approach is that each local filter runs with reduced number of states and the computation time for the whole system increases only linearly with the number of local sensors, thus significantly reduces the computational load compared to the centralized filter approach. This paper presents the technical aspect and performance analysis of the federated filter approach. Test results show that for a network of 100 reference stations, with the centralized approach, the network processing including ionospheric modeling and network ambiguity fixing needs approximately 60 hours to process 24 hours network data in a 3.06 GHz computer, which means it is impossible to run this network in real time. With the federated filter approach, only less than 1 hour is needed, 66 times faster than the centralized filter approach. The availability and reliability of network processing remain at the same high level.

• Journal of Microbiology
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• v.33 no.3
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• pp.215-221
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• 1995

S. coelicolor A3(2) cells were treated with various redox-cycling agents on nutrient agar plates and examined for their effect on the growth and differentiation. When treated with plumbagin, severe effect on cell viability was observed at concentrations above 250 $\mu$M. However, the surviving colonies differentiated normally. When treated with 100 $\mu$M paraquat, growth rate was decreased and morphological differentiation was inhibited, while the survival rate was maintained at about 100% even at 5 mM paraquat. Menadione or lawsone did not cause any visible changes at concentrations up to 1 mM. The effect of paraquat was also observed when it was added to nutrient agar plate before spore inoculation. Paraquat had also observed when it was added to nutrient agar plate before spore inoculation. Paraquat had no effect on colonies growing on R2YE agar plates. Among the components of R2YE medium selectively added to nutrient agar medium, CaCl$_2$ was found to have some protective function from the inhibitory effect of paraquat. As a first step to study the mechanism of the inhibitory effect of paraquat on differentiation, resistant mutants which sporulate well in the presence of paraquat were screened following UV mutagenesis. Three paraquat-resistant mutants were isolated with a frequency of 3 $\times$10${-5}$. Their mutation sites were determined by genetic crossings. All three mutations were mapped to a single locus near arg4 at about 1 o'clock on the genetic map of S. coelicolor A3(2).

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Journal of Radiation Protection and Research
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• v.2 no.1
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• pp.9-16
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• 1977

A simple method has been established for determining RaA, RaB and RaC concentrations in airborne dust. This is to evaluate the concentration from measurement of total alpha activities in three selected-time intervals after an air sample is taken from the membrane filter paper (mean pore size: $0.8{\mu}m$). As a preliminary trial, a time-variation of the concentrations has been determined using the single-filter method at the KAERI site (N. Lat. $37^{\circ}38'$ and E. Long $127^{\circ}15'$), Seoul, Korea. It appears that there is a large variation of the concentrations depending on the sampling time. Generally the highest value was observed in the morning that may coincide with the highest density of atmosphere in a day while the lowest value was obtained around fourteen o'clock.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.397-400
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• 2009

This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.11
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• pp.1462-1467
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• 2018

A number of algorithms for improving the image quality of low light images have been studied using a single image or multiple exposure images. The low light image is low in contrast and has a large amount of noise, which limits the identification of information of the subject. This paper proposes the hardware design of algorithms that improve the quality of low light image using 2 multiple exposure images taken with a dual camera. The proposed hardware structure is designed in real time processing in a way that does not use frame memory and line memory using transfer function. The proposed hardware design has been designed using Verilog and validated in Modelsim. Finally, when the proposed algorithm is implemented on FPGA using xc7z045-2ffg900 as the target board, the maximum operating frequency is 167.617MHz. When the image size is 1920x1080, the total clock cycle time is 2,076,601 and can be processed in real time at 80.7fps.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.251-253
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• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• Archives of Plastic Surgery
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• v.46 no.3
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• pp.221-227
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• 2019

Background Gynecomastia is a common condition that can cause severe emotional and physical distress in both young and older men. Patients in whom symptomatic recalcitrant gynecomastia persists for a long time are potential candidates for surgery. Methods From January 2014 to January 2016, 15 patients underwent correction of gynecomastia through a single 3-mm incision at our institution. Only patients with true gynecomastia underwent surgery with this new technique. Through the small incision, sharp dissection was performed in a clockwise and counterclockwise direction describing two half-circles. Health-related quality of life and aesthetic outcomes were evaluated using a modified version of the Breast Evaluation Questionnaire (BEQ). Results The patients' average age was 23.5 years (range, 18-28 years), and their average body mass index was $23.2kg/m^2$ (range, $19.2-25.3kg/m^2$). One case was unilateral and 14 cases were bilateral. The weight of glandular tissue resected from each breast ranged from 80 to 170 g. No excess skin was excised. Bleeding was minimal. The mean operating time was 25 minutes (range, 21-40 minutes). No complications were recorded. All lesions were histologically benign. The patients' average score was 3.5 (on a 5-point Likert scale) in all domains of the BEQ for themselves and their partners. Conclusions In this study, we demonstrated the safety and reliability of a new technique that allows mastectomy through an imperceptible 3-mm incision. We obtained high patient satisfaction scores using our surgical technique, and patients reported considerable improvement in their social, physical, and psychological well-being after surgery.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.32 no.3
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• pp.221-230
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• 2022

Objectives: The aim of this study is to evaluate the association between shiftwork and skeletal muscle mass index in a single university health check-up. Methods: We used data from 98,227 workers who answered in a special interview on health check-up at a local university hospital from 2014 to 2020. Pearson correlation analysis was conducted for comparing the association between skeletal muscle mass index and demographic and hematological variables in shiftwork and non-shiftwork groups. Mixed linear model analysis after controlling demographic and hematological variables was used to analyze the difference of skeletal muscle mass index between groups at every visit for seven years. Results: In linear regression analysis, the variables most significantly correlated with skeletal muscle index in both groups were shiftwork(p=0.049), BMI(p<0.001), hypertension(p=0.024), platelet(p<0.001), total protein (p<0.001), AST(p=0.028), ALT(p=0.003), ALP(p<0.001), total cholesterol(p=0.002), triglyceride(p=0.019), BUN (p=0.001), creatinine(p<0.001), and uric acid(p=0.002). After the adjustment for demographic and hematologic variables, the skeletal muscle mass index at every visit was decreased both in the shiftwork group and non-shiftwork group. The slope of the shiftwork group was -0.240 and non-shiftwork group -0.149, showing a significant difference (p<0.001). Conclusions: In the shiftwork group, the skeletal muscle mass index showed a tendency to decrease markedly over time compared to the non-shiftwork group. It is presumed that shift workers' skeletal muscle health was adversely affected by changes in the biological clock due to changes in wake-up and sleep patterns, and changes in food intake.

• Journal of the Korea Society of Computer and Information
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• v.14 no.10
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• pp.1-10
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• 2009

Precise branch predictor has a profound impact on system performance in modern processor architectures. Recent works show that prediction latency as well as prediction accuracy has a critical impact on overall system performance as well. However, prediction latency tends to be overlooked. In this paper, we propose Branch Pre-Prediction policy to tolerate branch prediction latency. The proposed solution allows that branch predictor can proceed its prediction without any information from the fetch engine, separating the prediction engine from fetch stage. In addition, we propose newly modified BTE structure to support our solution. The simulation result shows that proposed solution can hide most prediction latency with still providing the same level of prediction accuracy. Furthermore, the proposed solution shows even better performance than the ideal case, that is the predictor which always takes a single cycle prediction latency. In our experiments, IPC improvement is up to 11.92% and 5.15% in average, compared to conventional predictor system.