• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• Journal of the Korean Society for Marine Environment & Energy
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• v.9 no.4
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• pp.253-262
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• 2006

In this paper, collision analysis is carried out between two FRP fishing boats. A computer simulation with finite element method is used to accomplish this objective. At first, a detailed geometric model of the boat is constructed using 3-D CAD program. The formation of a finite element from a geometric data of the boats is carried out using HYPERMESH that is the commercial software for mesh generation and post processing. Twelve collision configurations are established by combining two kinds of contact angle($90^{\circ},\;135^{\circ}$) and three different speed(5, 10, 15knot) for small and large boats. Collision analysis is accomplished using DYNA3D. Stress distribution and deformation shape are investigated for each collision condition. In general, $90^{\circ}$ collision angle generate larger stress than $135^{\circ}$ case and the collision for two moving boats showed larger maximum stress than the case that one is moving and the other is stationary. When analysis is carried out until 150ms contact parts of two boats are broken for 10 and 15knot collision speed, in which maximum stress is larger than ultimate strength of the material.

• Journal of the Korea institute for structural maintenance and inspection
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• v.18 no.6
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• pp.60-71
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• 2014

Cable-stayed bridge, which is one of the representative long-spanned bridge, needs prompt maintenances when a stay cable is damaged because it may cause structural failure of the entire bridge. Many researches are being conducted to develop abnormal behavior detection algorithms for the purpose of shortening the reaction time after the occurrence of structural damage. To improve the accuracy of the damage detection algorithm, ample observation data from various kinds of damage responses is needed. However, it is difficult to measure an abnormal response by damaging an existing bridge, numerical simulation can be an effective alternative. In most previous studies, which simulate the damage responses of a cable-stayed bridge, the damages has been considered as a load variation without regard to its stiffness variation. The analyses of using these simplification could not calculate exact responses of damaged structure, though it may reserve a sufficient accuracy for the purpose of bridge design. This study suggests Gradual Bilinear Method (GBM) which simulate the damage responses of cable-stayed bridge considering the stiffness and mass variation, and develops an analysis program. The developed program is verified from the responses of a simple model. The responses of a existing cable-stayed bridge model are analyzed with respect to the fracture delay time and damage ratio. The results of this study can be used to develop and verify the highly accurate abnormal behavior detection algorithm for safety management of architecture/large structures.

• Journal of the Korean Association of Geographic Information Studies
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• v.19 no.2
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• pp.63-72
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• 2016

Closed-circuit television(CCTV) is a facility that forms the backbone of the ubiquitous services provided by the Integrated Management Center of the Ministry of Land, Infrastructure and Transport and the Integrated Control Center of the Ministry of the Interior. However, it is installed and managed according to different laws, as it is operated and managed by each department. Moreover, because there are no regulatory grounds for unified management of CCTV, each municipality responsible for the actual management manages it based on the individual standards of each department. Thus, the purpose of this study is to develop a standardized management form to establish an integrated management plan. The author inspected the existing situation by examining the legal system and public data and through hands-on worker interviews, and discovered the managed element by reviewing the specifications of the bidding system. The management form for integrated management comprises the above requirements along with the management histories and linkage of intelligent facilities. A uniform management form for integrated management containing specifications of the CCTVs installed by various departments is created, and is easily searched for facilities to check requirements for joint use. The result of this study can contribute to building the database of facility management system for integrated management of facilities at the integrated management center as well as for a detailed simulation of the selection of location of CCTV depending on the CCTV's specifications.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.28-34
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• 2012

Various feature extraction algorithms are widely applied to real-time image processing applications for extracting significant features from images. Feature extraction algorithms are mostly combined with image processing algorithms mostly for image tracking and recognition. Feature extraction function is used to supply feature information to the other image processing algorithms and it is mainly implemented in a preprocessing stage. Nowadays, image processing applications are faced with embedded system implementation for a real-time processing. In order to satisfy this requirement, it is necessary to reduce execution time so as to improve the performance. Reducing the time for executing a feature extraction function dose not only extend the execution time for the other image processing algorithms, but it also helps satisfy a real-time requirement. This paper explains FAST (Feature from Accelerated Segment Test algorithm) of E. Rosten and presents FPGA-based embedded hardware accelerator architecture. The proposed acceleration scheme can be implemented by using approximately 2,217 Flip Flops, 5,034 LUTs, 2,833 Slices, and 18 Block RAMs in the Xilinx Vertex IV FPGA. In the Modelsim - based simulation result, the proposed hardware accelerator takes 3.06 ms to extract 954 features from a image with $640{\times}480$ pixels and this result shows the cost effectiveness of the propose scheme.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.40 no.4
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• pp.191-202
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• 2017

The purpose of this study is to develop an engineer competency model using Analytical Hierarchy Process (AHP) to improve the national technical qualification system. Korea has managed technical human resources at the government level through the operation of a national technical qualification system that certifies engineers with national certificates or technical grades by laws. However, there have been increasing concerns that the government system is separated from global standards and does not reflect an engineer's comprehensive capabilities. For these reasons, the new architecture of the system has been continuously discussed and becomes a major policy issue of the Korean government. For the development of the engineer competency model, domestic and global models were separately structured using 554 valid questionnaires with a consistency ratio (CR) of 0.1 or less. The relative importance of engineer competency factors in a domestic model was career (0.383), qualification (0.253), academic degree (0.195), and job training (0.169) whereas the order in the global model was career (0.308), global ability (0.237), job training (0.175), domestic qualification (0.147), and academic degree (0.134). The results of AHP analysis indicated that the evaluation factors and methods recognized by engineers were different from a current government model focusing on domestic qualifications. There was also perceptual difference in the importance of engineer evaluation factors between groups depending on the type of organizations and markets. This means that it is necessary to reflect the characteristics of organizations and markets when evaluating engineer competency. Based on AHP analysis and literature reviews, this paper discussed how to develop a new engineer competency index (ECI) and presented two effective index models verified by simulation test using 59,721 engineers' information. Lastly, the paper discussed major findings of our empirical research and proposed policy alternatives for the improvement of a national engineer qualification system. The paper contributes to the management of technical human resources since it provides quantitative competency models that are objectively developed by reflecting market recognition and can be effectively used by the policy makers or firms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.10-17
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• 2007

It opens a new horizon on spintronics for the potential application of MTJ as a universal logic element, to employ the magneto-logic in substitution for the transistor-based logic device. The magneto-logic based on the MTJ element shows many potential advantages, such as high density, and nonvolatility. Moreover, the MTJ element has programmability and can therefore realize the full logic functions just by changing the input signals. This magneto-logic using MTJ elements can embody the reconfigurable circuit to overcome the rigid architecture. The established magneto-logic element has been designed and fabricated on a triple-layer MTJ. We present a novel magneto-logic structure that consists of a single layer MTJ and a current driver, which requires less processing steps with enhanced functional flexibility and uniformity. A 4-bit gray counter is designed to verify the magneto-logic functionality of the proposed single-layer MTJ and the simulation results are presented with the HSPICE macro-model of MTJ that we have developed.

• Journal of KIISE:Software and Applications
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• v.29 no.5
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• pp.326-335
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• 2002

Recently there have been a number of researches to provide code mobility to lazy functional language (LFL) programs by translating LFL programs to Java programs. These approaches are basically baled on architectural similarities between abstract machines of LFLs and Java. The abstract machines of LFLs and Java programming language, Spineless Tagless G-Machine(STGM) and Java Virtual Machine(JVM) respectively, share important common features such as built- in garbage collector and stack machine architecture. Thus, we can provide code mobility to LFLs by translating LFLs to Java utilizing these common features. In this paper, we propose a new translation scheme which fully utilizes architectural common features between STGM and JVM. By redefining STGM as an eval-apply evaluation model, we have defined a new translation scheme which utilizes Java Virtual Machine Stack for function evaluation and totally eliminates stack simulation which causes array manipulation overhead in Java. Benchmark program translated to Java programs by our translation scheme run faster on JDK 1.3 than those translated by the previous schemes.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.557-562
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• 2005

Throughput and latency of interconnection network are important factors of the performance of multiprocessor systems. The dual-link CC-NUMA architecture using point-to-point unidirectional link is one of the popular structures in high-end commercial systems. In terms of optimal path between nodes, several paths exist with the optimal hop count by its native multi-path structure. Furthermore, transaction latency between nodes is affected by congestion of links on the transaction path. Hence the transaction latency may get worse if the transactions make a hot spot on some links. In this paper, I propose a dynamic transaction routing algorithm that maintains the balanced link utilization with the optimal path length, and I compare the performance with the fixed path method on the dual-link CC-NUMA systems. By the proposed method, the link competition is alleviated by the real-time path selection, and consequently, dynamic transaction algorithm shows a better performance. The program-driven simulation results show $1{\~}10\%$ improved fluctuation of link utilization, $1{\~}3\%$ enhanced acquirement of link, and $1{\~}6\%$ improved system performance.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.479-488
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• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.