• 제목/요약/키워드: simulation/implementation

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Stretched-Exponential 형태의 문턱전압 이동 모델의 SPICE구현 (Implementation of Stretched-Exponential Time Dependence of Threshold Voltage Shift in SPICE)

  • 정태호
    • 반도체디스플레이기술학회지
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    • 제19권1호
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    • pp.61-66
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    • 2020
  • Threshold voltage shift occurring during operation is implemented in a SPICE simulation tool. Among the shift models the stretched-exponential function model, which is frequently observed from both single-crystal silicon and thin-film transistors regardless of the nature of causes, is selected, adapted to transient simulation, and added to BSIM4 developed by BSIM Research Group at the University of California, Berkeley. The adaptation method used in this research is to select degradation and recovery models based on the comparison between the gate and threshold voltages. The threshold voltage shift is extracted from SPICE transient simulation and shows the stretched-exponential time dependence for both degradation and recovery situations. The implementation method developed in this research is not limited to the stretched-exponential function model and BSIM model. The proposed method enables to perform transient simulation with threshold voltage shift in situ and will help to verify the reliability of a circuit.

디지털 조선소 구축 및 활용을 위한 모델링 및 시뮬레이션 프레임워크 구축 방법론 (Simulation Modeling Methodology and Simulation Framework for a Construction of a Digital Shipyard)

  • 우종훈;오대균;권영대;신종계;서주노
    • 대한조선학회논문집
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    • 제42권4호
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    • pp.411-420
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    • 2005
  • World leading company and research centers have invested much cost and effort into a PLM and digital manufacturing field to obtain their own competitiveness. We have been trying to apply a digital manufacturing, especially simulation to ship production process as a part of PLM implementation for a shipyard. A shipbuilding production system and processes have a complexity and a peculiarity different from other kinds of production systems. So, new analysis and modeling methodology is required to implement digital shipyard. which is a digital manufacturing system for a shipbuilding company. This paper suggests an analysis and simulation modeling methodologies for an implementation of a digital shipyard. New methodologies such as a database-merged simulation, a distributed simulation, a modular simulation with a model library and a 3-tire simulation framework are developed.

두부손상 시물레이션 시나리오 개발 및 수행평가 (Development of Scenario and Evaluation on the Implementation of Head Trauma Simulation)

  • 백미례
    • 한국응급구조학회지
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    • 제15권2호
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    • pp.55-66
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    • 2011
  • Purpose: The purpose of this study was to develop a scenario and evaluate the performance of paramedic students in head trauma simulation education. Method: This study selected a refined head trauma scenario that was developed by graduate students during class from september to November, 2010. Evaluation on implementation of head trauma simulation was conducted on seventeen paramedic students divided into four groups during November, 2010. Results: 1. The head trauma scenario was developed according to the patient assessment for approximately 10 minutes. It contained scene size-up, initial assessment and intervention, rapid trauma assessment and intervention, and decision of transfer. 2. The average time turned out to be 9 min and 36 sec after simulation learning. Total mean score in simulation performance was 2.20, the highest score was 2.44 in initial assessment and intervention, and the lowest score was 1.5 in decision of transfer. 3. Confidence mean was high with the score of 1.0. Conclusion: The finding of this study demonstrate that the simulation education can improve problem-solving ability and critical thinking, and increase the confidence in prehospital emergency care; therefore, simulation may be the new effective paramedic education strategy and simulation learning is needed for further development of various scenarios.

운전자 교육을 위한 PC 기반의 굴삭기 시뮬레이터의 개발 (Development of a PC-based Excavator Simulator for Operator Training)

  • 한경숙;황세훈
    • 한국시뮬레이션학회논문지
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    • 제9권1호
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    • pp.83-91
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    • 2000
  • Vehicle simulators provide an effective and safe environment for training operators. Many vehicle simulators have been developed but only a few have reached the stage of widely available tools; these tools are usually expensive and run on workstations only We have developed a low-cost, PC-based excavator simulator for training operators. Currently the simulator is dedicated to operating the boom, Em, bucket, and driver's cabin for digging by the action of the operator on two joysticks. This paper presents the implementation of the excavator simulator and some implementation results.

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DEVS 다이어그램 기반 이산사건 시뮬레이션 소프트웨어 구현 및 정적 검증기법: 실용적 접근방법 (Implementation and Static Verification Methodology of Discrete Event Simulation Software based on the DEVS Diagram: A Practical Approach)

  • 송해상
    • 한국시뮬레이션학회논문지
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    • 제27권3호
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    • pp.23-36
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    • 2018
  • 이산사건시스템명세(DEVS) 형식론은 이산사건시스템을 모듈러하고 계층적으로 모델링할 수 있는 잘 정의된 의미론을 제공하고 있어 이산사건시스템 모델링 시뮬레이션 (M&S)에 많이 사용되어 왔다. 이러한 수학적 표현 대신에 DEVS 다이어그램은 복잡한 시스템을 보다 직관적이며 편리한 표현력을 제공한다. 본 논문은 DEVS 다이어그램을 이용하여 표현된 모델을 시뮬레이션 코드로 체계적으로 구현하며 검증하는 DEVS 클린룸 프로세스를 제안하였다. 구체적으로, 주어진 다이어그램 모델의 적합성 검사, 테이블 DEVS 모델로의 변환, 마지막으로 시뮬레이션 소스코드로 변환하는 방법과 역으로 추적성을 기반으로 한 검사기법을 통해 정적 검증하는 구체적인 방법을 제시하였다. 간단한 예제를 통해 제안된 프로세스를 적용하는 구체적인 방법을 설명하였으며, 적용사례 통해 제안된 기법이 실용적으로 적용 가능한 효과적인 프로세스임을 확인하였다.

위성 통신용 리턴 링크 복조기의 성능 개선에 관한 연구 (A Study about Performance Improvement of Return Link Demodulator for Satellite Communication)

  • 왕도휘;오덕길
    • 한국위성정보통신학회논문지
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    • 제7권1호
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    • pp.92-96
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    • 2012
  • 본 논문은 복잡한 신호처리 기능을 포함하는 리턴 링크 복조 알고리즘이 낮은 SNR에서도 안정적으로 동작하도록 하기 위해 하드웨어에 적합하도록 설계하여 HDL로 구현하는 것을 목적으로 한다. 모의실험 결과 Uncoded BER $10^{-3}$ 지점에서의 Es/$N_0$가 이상적인 QPSK 신호 대비 0.5dB 이내로의 성능개선을 이룬 것을 확인할 수 있다. 또한 이에 대한 Fixed-Point Simulation 및 HDL 구현 성능이 모의실험 대비 차이가 없음을 확인할 수 있다.

STUDY OF NEW CAST-IN-PLACE MORTAR WALL FOR HOUSE CONSTRUCTION COMPARED TO BRICK AND MORTAR-BLOCK SYSTEM (A SIMULATION IN DIFFERENT AREAS)

  • Arief Setiawan Budi Nugroho;Shin-ei Takano
    • 국제학술발표논문집
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    • The 3th International Conference on Construction Engineering and Project Management
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    • pp.196-202
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    • 2009
  • Study from Yogyakarta earthquake reconstruction program, cast-in-place wall using fix-size formwork system (Old-CIP) has offered a good alternative for house construction. A simulation has also confirmed that this system using mortar as the main material can provide cheapest cost and lowest total man power compared to conventional wall construction technique: brick or mortar-block wall. This paper presents the new wall construction technique: full size cast-in-place wall (New-CIP). The detail of how this new technique implemented is described. In addition, considering that material and labor cost in one area is different to others, cost analysis for different resources prices and wages of three cities are taken into a simulation. The analysis is aimed to distinguish the implementation feasibility of New-CIP system compared to the four common wall systems. Finally, its implementation resistance is also discussed.

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단일 톤 신호의 페이저 측정기법 및 FPGA구현 (An FPGA implementation of phasor measurement algorithm for single-tone signal)

  • 안병선;김종윤;장태규
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(4)
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    • pp.171-174
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    • 2002
  • This paper presents an implementation method of phasor measurement device, which is based on the FPGA implementation of the sliding-DFT The design is verified by the timing simulation of its operation. The error effect of coefficient approximation and frequency deviation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations.

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Fast Implementation of the Progressive Edge-Growth Algorithm

  • Chen, Lin;Feng, Da-Zheng
    • ETRI Journal
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    • 제31권2호
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    • pp.240-242
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    • 2009
  • A computationally efficient implementation of the progressive edge-growth algorithm is presented. This implementation uses an array of red-black (RB) trees to manage the layered structure of check nodes and adopts a new strategy to expand the Tanner graph. The complexity analysis and the simulation results show that the proposed approach reduces the computational effort effectively. In constructing a low-density parity check code with a length of $10^4$, the RB-tree-array-based implementation takes no more 10% of the time required by the original method.

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