• 한국재료학회지
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• 제28권2호
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• pp.124-128
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• 2018

N-type porous silicon (PS) layers and thermally oxidized PS layers have been characterized by various measuring techniques such as photoluminescence (PL), Raman spectroscopy, IR, HRSEM and transmittance measurements. The top surface of PS layer shows a stronger photoluminescence peak than its bottom part, and this is ascribed to the difference in number of fine silicon particles of 2~3 nm in diameter. Observed characteristics of PL spectra are explained in terms of microstructures in the n-type PS layers. Common features for both p-type and n-type PS layers are as follows: the parts which can emit visible photoluminescence are not amorphous, but crystalline, and such parts are composed of nanocrystallites of several nm's whose orientations are slightly different from Si substrate, and such fine silicon particles absorb much hydrogen atoms near the surfaces. Light emission is strongly dependent on such fine silicon particles. Photoluminescence is due to charge carrier confinement in such three dimensional structure (sponge-like structure). Characteristics of visible light emission from n-type PS can be explained in terms of modification of band structure accompanied by bandgap widening and localized levels in bandstructure. It is also shown that hydrogen and oxygen atoms existing on residual silicon parts play an important role on emission stability.

• ETRI Journal
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• 제17권4호
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Tribology and Lubricants
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• 제33권6호
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• pp.282-287
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• 2017

SU-8 is an epoxy-type photoresist widely used for the fabrication of high-aspect-ratio (HAR) micro-structures in micro-electro-mechanical systems (MEMS). To fabricate highly integrated structures, chemical mechanical polishing (CMP) has emerged as the preferred manufacturing process for planarizing the MEMS structure. In SU-8 CMP, an oxidizer decomposes organic impurities and particles in the CMP slurry remove the chemically reacted surface of SU-8. To fabricate HAR microstructures using the CMP process, the adhesion between SU-8 and substrate material is important to avoid the delamination of the SU-8 film caused by the mechanical-dominant material removal characteristic. In this study, the friction force during the CMP process is measured with a CMP monitoring system to detect the delamination phenomenon and investigate the delamination of the SU-8 film from the silicon substrate under various pressure conditions. The increase in applied pressure causes an increase in the frictional force and wafer-edge stress concentration. The frictional force measurement shows that the friction force changes according to the delamination phenomenon of the SU-8 film, and that it is possible to monitor the delamination phenomenon during the SU-8 CMP process. The delamination at a high applied pressure is explained by the effect of stress distribution and pad deformation. Consequently, it is necessary to control the pressure of polishing, which can avoid the delamination in SU-8 CMP.

• E2M - 전기 전자와 첨단 소재
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• 제11권11호
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• pp.22-27
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• 1998

We have investigated the effect of an ion shower doping of the laser annealed poly-Si films at an elevated substrate temperatures. The substrate temperature was varied from room temperature to 300$^{\circ}C$ when the poly-Si film was doped with phosphorus by a non-mass-separated ion shower. Optical, structural, and electrical characterizations have been performed in order to study the effect of the ion showering doping. The sheet resistance of the doped poly-Si films was decreased from7${\times}$106 $\Omega$/$\square$ to 700 $\Omega$/$\square$ when the substrate temperature was increased from room temperature to 300$^{\circ}C$. This low sheet resistance is due to the fact that the doped film doesn't become amorphous but remains in the polycrystalline phase. The mildly elevated substrate temperature appears to reduce ion damages incurred in poly-Si films during ion-shower doping. Using the ion-shower doping at 250$^{\circ}C$, the field effect mobility of 120 $\textrm{cm}^2$/(v$.$s) has been obtained for the n-channel poly-Si TFTs.

• 원예과학기술지
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• 제32권2호
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• pp.142-148
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• 2014

Effect of silicon (Si) nutrition on growth and temperature stress tolerance of Nephrolepis exaltata 'Corditas' grown in a soilless substrate was examined. In vitro-grown acclimatized plantlets were transplanted into the pots containing a coir-based substrate. A nutrient solution containing 0, 50, or $100mg{\cdot}L^{-1}$ Si was supplied through a drip-irrigation system. After 5 months of cultiv ation, S i-treated and -untreated p lants were grown at 10, 25, or $40{\pm}1^{\circ}C$ under a 12 h photoperiod with $530{\mu}mol{\cdot}m^{-2}{\cdot}s^{-1}$ PPFD and 60% RH. After 7 days, chlorophyll content and chlorophyll fluorescence parameters were measured. Silicon nutrition had a negative effect on growth characteristics of N. exaltata 'Corditas'. However, Si-treated plants had more tolerance to temperature stress than the control plants. The Fv/Fm value was not significantly different when the plants were exposed to $25^{\circ}C$. However, significant difference in Fv/Fm was recorded when plants were exposed to 10 or $40^{\circ}C$. Thus, Fv/Fm could be used as an indicator of low and high temperature tolerance in ferns. The present study also suggests that application of Si may be used to enhance temperature tolerance of ferns.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.429-429
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• 2012

To investigate the gettering effect of B-doped n-type monocrystalline silicon wafer, we made the p-n junction by diffusing boron into n-type monocrystalline Si substrate and then oxidized the boron doped n-type monocrystalline silicon wafer by in-situ wet and dry oxidation. After oxidation, the minority carrier lifetime was measured by using microwave photoconductance and the sheet resistance by 4-point probe, respectively. The junction depth was analyzed by Secondary Ion Mass Spectrometry (SIMS). Boron diffusion reduced the metal impurities in the bulk of silicon wafer and increased the minority carrier lifetime. In the case of wet oxidation, the sheet resistance value of ${\sim}46{\Omega}/{\Box}$ was obtained at $900^{\circ}C$, depostion time 50 min, and drive-in time 10 min. Uniformity was ~7% at $925^{\circ}C$, deposition time 30 min, and drive-in time 10 min. Finally, the minority carrier lifetime was shown to be increased from $3.3{\mu}s$ for bare wafer to $21.6{\mu}s$ for $900^{\circ}C$, deposition 40 min, and drive-in 10 min condition. In the case of dry oxidation, for the condition of 50 min deposition, 10 min drive-in, and O2 flow of 2000 SCCM, the minority carrier lifetime of 16.3us, the sheet resistance of ${\sim}48{\Omega}/{\Box}$, and uniformity of 2% were measured.

• 한국표면공학회지
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• 제54권3호
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• pp.133-138
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• 2021

Ternary Ti-X-N coatings, where X = Al, Si, Cr, O, etc., have been widely used for machining tools and cutting tools such as inserts, end-mills, and etc. Ti-Al-N-O coatings were deposited onto silicon wafer and WC-Co substrates by a cathodic arc evaporation (CAE) technique at various negative substrate bias voltages. In this study, the influence of substrate bias voltages during deposition on the microstructure and mechanical properties of Ti-Al-N-O coatings were systematically investigated to optimize the CAE deposition condition. Based on results from various analyses, the Ti-Al-N-O coatings prepared at substrate bias voltage of -80 V in the process exhibited excellent mechanical properties with a higher compressive residual stress. The Ti-Al-N-O (-80 V) coating exhibited the highest hardness around 30 GPa and elastic modulus around 303 GPa. The improvement of mechanical properties with optimized bias voltage of -80 V can be explained with the diminution of macroparticles, film densification and residual stress induced by ion bombardment effect. However, the increasing bias voltage above -80 V caused reduction in film deposition rate in the Ti-Al-N-O coatings due to re-sputtering and ion bombardment phenomenon.

• Transactions on Electrical and Electronic Materials
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• 제17권4호
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• pp.204-207
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• 2016

Experimental study of UV-irradiated O₂/H₂ gas phase cleaning for PMMA (Polymethylmethacrylate) removal is carried out in a load-locked reactor equipped with a UV lamp and PBN heater. UV enhanced O₂/H₂ gas phase cleaning removes polymethylmethacrylate (PMMA) better at lower process pressure with higher content of H₂. O₂ gas compete for UV (184.9 nm) absorption with PMMA producing O₃, O(¹D) and lower dissociation of PMMA. In our experimental conditions, etching reaction of PMMA at the substrate temperature between 75℃ and 125℃ had activation energy of about 5.86 kcal/mol indicating etching was controlled by surface reaction. Above the 180℃, PMMA removal was governed by a supply of reaction gas rather than by substrate temperature.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.975-978
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• 1999

The transmission line effects of IC interconnects have a substantial effect on a hish-speed VLSI circuit performance. The effective transmission lime parameters are changed with the increase of the operation frequency because of the skin of the skin effect, proximity effect, and silicon substrate. A new signal delay estimation methodology based on the RLC-distributed circuit model is presented ［2］. The methodology is demonstrated by using SPICE simulation and a high-frequency experiment technique.

• ETRI Journal
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• 제33권1호
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• pp.13-17
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• 2011

A highly miniaturized on-chip $180^{\circ}$ hybrid employing periodic ground strip structure (PGSS) was realized on a silicon radio frequency integrated circuit. The PGSS was placed at the interface between $SiO_2$ film and silicon substrate, and it was electrically connected to top-side ground planes through the contacts. Owing to the short wavelength characteristic of the transmission line employing the PGSS, the on-chip $180^{\circ}$ hybrid was highly miniaturized. Concretely, the on-chip $180^{\circ}$ hybrid exhibited good radio frequency performances from 37 GHz to 55 GHz, and it was 0.325 $mm^2$, which is 19.3% of a conventional $180^{\circ}$ hybrid. The miniaturization technique proposed in this work can be also used in other fields including compound semiconducting devices, such as high electron mobility transistors, diamond field effect transistors, and light emitting diodes.