• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.8
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• pp.505-509
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• 2016

We have investigated the characteristics of amorphous silicon (a-Si) thin-film solar cell by inserting barrier layer. The conversion efficiency of a-Si thin-film solar cells on graphite substrate shows nearly zero because of the surface roughness of the graphite substrate. To enhance the performance of solar cells, the surface morphology of the back side were modified by changing the barrier layer on graphite. The surface roughness of graphite substrate with the barrier layer grown by plasma enhanced chemical vapor deposition (PECVD) reduced from ~2 um to ~75 nm. In this study, the combination of the barrier layer on graphite substrate is important to increase solar cell efficiency. We achieved ~ 7.8% cell efficiency for an a-Si thin-film solar cell on graphite substrate with SiNx/SiOx stack barrier layer.

• Journal of Korean Vacuum Science & Technology
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• v.2 no.1
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• pp.49-54
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• 1998

The effect of deposition paratmeters on the solid-phase crystallization of amorphous silicon films deposited by plasma-enhanced chemical vapor deposition has been investigated by x-ray diffraction. The amorphous silicon films were prepared on Si(100) wafers using SiH4 gas with and without H2 dilution at the substrate temperatures between 12$^{\circ}C$ and 38$0^{\circ}C$. The R. F. powers and the deposition pressures were also varied. After crystallizing at $600^{\circ}C$ for 24h, the films exhibited (111), (220), and (311) x-ray diffraction peaks. The (111) peak intensity increased as the substrate temperature decreased, and the H dilution suppressed the crystallization. Increasing R.F. powers within the limits of etching level and increasing deposition pressures also have enhanced the peak intensity. The peak intensity was closely related to the deposition rate, which may be an indirect indicator of structural disorder in amorphous silicon films. Our results are consistent with the fact that an increase of the structural disorder I amorphous silicon films enhances the grain size in the crystallized films.

• Journal of the Korean institute of surface engineering
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• v.26 no.3
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• pp.115-120
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• 1993

Aluminum thin films were deposited on the silicon substrate by the pyrolysis of TrilsoButylAluminum (TIBA) in a cold wall LPCVD reactor. The effect of substrate on the surface topograply and the decomposition reaction was investigated. The activation energy for the decomposition of TIBA was turned out to be 1 eV from the Arrhenious plot. The surface topography of the CVD aluminum could be improved by the application of thin metal film, which was in-situ deposited on the silicon prior to CVD process.

• Korean Journal of Materials Research
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• v.14 no.7
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• pp.477-481
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• 2004

High quality polycrystalline silicon is very critical part of the high quality thin film transistor(TFT) for display devices. Metal induced lateral crystallization(MILC) is one of the most successful technologies to crystallize the amorphous silicon at low temperature(below $550^{\circ}C$) and uses conventional and large glass substrate. In this study, we observed that the MILC behavior changed with abrupt variation of the amorphous silicon active pattern width. We explained these phenomena with the novel MILC mechanism model. The 10 nm thick Ni layers were deposited on the glass substrate having various amorphous silicon patterns. Then, we annealed the sample at $550^{\circ}C$ with rapid thermal annealing(RTA) apparatus and measured the crystallized length by optical microscope. When MILC progress from narrow-width-area(the width was $w_2$) to wide-width-area(the width was $w_1$), the MILC rate decreased dramatically and was not changed for several hours(incubation time). Also the incubation time increased as the ratio, $w_1/w_2$, get larger. We can explain these phenomena with the tensile stress that was caused by volume shrinkage due to the phase transformation from amorphous silicon to crystalline silicon.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.4
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• pp.169-172
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• 2003

Silicon nanocrystalline thin films on p-type (100) silicon substrate have been fabricated by pulsed laser deposition technique using a Nd:YAG laser with the wavelength of 355, 532, and 1064 nm. The base vacuum in the chamber was down to $10^-6$ Torr and the laser energy densities were 1.0~3.0 J/$\textrm{cm}^2$ After deposition, silicon nanocrystalline thin films have been annealed at nitrogen gas. Strong Blue and green luminescence from silicon nanocrystalline thin films have been observed at room temperature by photoluminescence and its peak energies shift to green when the wavelength is increased from 355 to 1064 nm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.153-153
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• 2009

We investigated the dependence of the memory margin of the Cap-less memory cell on the strain of top silicon channel layer and also compared kink effect of strained Cap-less memory cell with the conventional Cap-less memory cell. For comparison of the characteristic of the memory margin of Cap-less memory cell on the strain channel layer, Cap-less transistors were fabricated on fully depleted strained silicon-on-insulator of 0.73-% tensile strain and conventional silicon-on-insulator substrate. The thickness of channel layer was fabricated as 40 nm to obtain optimal memory margin. We obtained the enhancement of 2.12 times in the memory margin of Cap-less memory cell on strained-silicon-on-insulator substrate, compared with a conventional SOI substrate. In particular, much higher D1 current of Cap-less memory cell was observed, resulted from a higher drain conductance of 2.65 times at the kink region, induced by the 1.7 times higher electron mobility in the strain channel than the conventional Cap-less memory cell at the effective field of 0.3MV/cm. Enhancement of memory margin supports the strained Cap-less memory cell can be promising substrate structures to improve the characteristics of Cap-less memory cell.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.18 no.1
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• pp.38-44
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• 2008

Contiuous c-oriented zeolite MFI films $(<35{\mu}m)$ were prepared by hydrothermal secondary growth of silicalite-1 seed crystal in the surface of alumina porous substrate and silicon substrate. The supported films were characterized with scanning electron microscopy and X-ray diffraction. Effect of substrate surface roughness were investigated and a mechanism for c-oriented film formation and characteristic dom-like defects formation which is observed after seeding growth was discussed. The roughness of substrate plays an important role.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.413-413
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• 2009

Silicon nanowires (Si NWs)-based top-gate field-effect transistors (FETs) are constructed by using Si NWs transferred onto flexible plastic substrates. Si NWs are obtained from the silicon wafers using photolithography and anisotropic etching process, and transferred onto flexible plastic substrates. To evaluate the electrical performance of the silicon nanowires, we examined the output and transfer characteristics of a top-gate field-effect transistor with a channel composed of a silicon nanowire selected from the nanowires on the plastic substrate. From these FETs, a field-effect mobility and transconductance are evaluated to be $47\;cm^2/Vs$ and 272 nS, respectively.

• Journal of the Korean Ceramic Society
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• v.38 no.9
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• pp.846-852
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• 2001

A two-dimensional Monte Carlo simulation has been used to investigate the effect of the reaction temperature on the formation of the silicon carbide conversion layer near the surface of graphite substrate The carbothermal reduction of silica is the reaction mechanism of silicon carbide formation on graphite substrate by chemical vapor reaction methods. The chemical composition of silicon carbide conversion layer gradually changes from carbon to silicon carbide because gaseous reactants diffuse through micropores within graphite substrate and react with carbon at the surface of inner pores. The simulation was carried out under the condition of reaction temperature at 1900K, 2000K, 2100K and 2200K for 500MCS. It was found from the results of simulation that the thickness of silicon carbide conversion layer increases with reaction temperature.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.387-392
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• 2018

Static characteristics of SiC (silicon carbide) lateral p-i-n diodes implemented on semi-insulating substrate without an epitaxial layer are inVestigated. On-axis SiC HPSI (high purity semi-insulating) and VDSI (Vanadium doped semi-insulating) substrates are used to fabricate the lateral p-i-n diode. The space between anode and cathode ($L_{AC}$) is Varied from 5 to $20{\mu}m$ to inVestigate the effect of intrinsic-region length on static characteristics. Maximum breakdown Voltages of HPSI and VDSI are 1117 and 841 V at $L_{AC}=20{\mu}m$, respectiVely. Due to the doped Vanadium ions in VDSI substrate, diffusion length of carriers in the VDSI substrate is less than that of the HPSI substrate. A forward Voltage drop of the diode implemented on VDSI substrate is 12 V at the forward current of $1{\mu}A$, which is higher than 2.5 V of the diode implemented on HPSI substrate.