• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.499-499
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• 2011

Silicon nanowires (Si NWs) have been extensively studied for nanoelectronics owing to their unique optical and electrical properties different from those of bulk silicon. For the development of Si NW devices, better understanding of oxidation behavior in Si NWs would be an important issue. For example, it is widely known that atomic scale roughness at the dielectric (SiOx)/channel (Si) interface can significantly affect the device performance in the nano-scale devices. However, the oxidation process at the atomic-scale is still unknown because of its complexity. In the present work, we investigated the oxidation behavior of Si NW in atomic scale by simulating the dry oxidation process using a reactive molecular dynamics simulation technique. We focused on the residual stress evolution during oxidation to understand the stress effect on oxidation behavior of Si NWs having two different diameters, 5 nm and 10 nm. We calculated the charge distribution according to the oxidation time for 5 and 10 nm Si NWs. Judging from this data, it was observed that the surface oxide layer started to form before it is fully oxidized, i.e., the active diffusion of oxygen in the surface oxide layer. However, it is well-known that the oxide layer formation on the Si NWs results in a compressive stress on the surface which may retard the oxygen diffusion. We focused on the stress evolution of Si NWs during the oxidation process. Since the surface oxidation results in the volume expansion of the outer shell, it shows a compressive stress along the oxide layer. Interestingly, the stress for the 10 nm Si NW exhibits larger compressive stress than that of 5 nm Si NW. The difference of stress level between 5 an 10 anm Si NWs is approximately 1 or 2 GPa. Consequently, the diameter of Si NWs could be a significant factor to determine the self-limiting oxidation behavior of Si NWs when the diameter was very small.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.149-155
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• 1996

A new technique wasdeveloped which obtains selectively the htick fully recessed oxidized porous silicon layer (OPSL) with good dielectric property. The porous silicon layer was ocnverted to thick fully recessed oxide (FRO) with 3-step (1${\mu}$m, 1.5${\mu}$m, 1.8${\mu}$m) by multi-step thermal oxidation (after 400$^{\circ}$C, 1 hour by dry oxidation, 700$^{\circ}$C, 1 hour and then 1100$^{\circ}$C, 1 hour by wet oxidation). The breakdwon field of the FRO was about 2.5MV/cm and the leakage current was several pA ~ 100 pA in the range of 0 of 90 pF. The progress of oxidation of a porous silicon layer was studied by examining the infrared abosrption spectra. The refractive index (1.51) of the fRO, which was measured by ellipsometer, was comparable to that of the thermally grown silicon dioxide (1.46). The etching rate (1600${\AA}$/min) of the FRO was also almost equal to that of the thermal oxide.

• Korean Chemical Engineering Research
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• v.46 no.2
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• pp.408-413
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• 2008

In this work, the use of LPRTO (low pressure rapid thermal oxidation) and remote plasma oxidation was evaluated for the preparation of ultra thin silicon oxide layer with less than 5 nm. The silicon oxide thickness grown by LPRTO was rapidly increased and saturated. The maximum thickness could be controlled at about 5 nm. As RF power and oxygen flow rate at a remote plasma oxidation increased, the behavior of oxide growth was almost the same as that of LPRTO. The oxide thickness of 4 nm was the maximum obtained by a remote plasma oxidation in this work. The quality of silicon oxide grown by LPRTO was comparable to the thermally grown conventional oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.429-429
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• 2012

To investigate the gettering effect of B-doped n-type monocrystalline silicon wafer, we made the p-n junction by diffusing boron into n-type monocrystalline Si substrate and then oxidized the boron doped n-type monocrystalline silicon wafer by in-situ wet and dry oxidation. After oxidation, the minority carrier lifetime was measured by using microwave photoconductance and the sheet resistance by 4-point probe, respectively. The junction depth was analyzed by Secondary Ion Mass Spectrometry (SIMS). Boron diffusion reduced the metal impurities in the bulk of silicon wafer and increased the minority carrier lifetime. In the case of wet oxidation, the sheet resistance value of ${\sim}46{\Omega}/{\Box}$ was obtained at $900^{\circ}C$, depostion time 50 min, and drive-in time 10 min. Uniformity was ~7% at $925^{\circ}C$, deposition time 30 min, and drive-in time 10 min. Finally, the minority carrier lifetime was shown to be increased from $3.3{\mu}s$ for bare wafer to $21.6{\mu}s$ for $900^{\circ}C$, deposition 40 min, and drive-in 10 min condition. In the case of dry oxidation, for the condition of 50 min deposition, 10 min drive-in, and O2 flow of 2000 SCCM, the minority carrier lifetime of 16.3us, the sheet resistance of ${\sim}48{\Omega}/{\Box}$, and uniformity of 2% were measured.

• Journal of the Korean Ceramic Society
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• v.35 no.6
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• pp.535-542
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• 1998

SOI(silicon oninsulator) was fabricated through the direct bonding of a hydrophilized single crystal Si wafer and a thermally oxidized SiO2 thin film to investigate the stacking faults in silicon at the Si/SiO2 in-terface. At first the oxidation kinetics of SiO2 thin film and the stacking fault distribution at the oxidation interface were investigated. The stacking faults could be divided into two groups by their size and the small-er ones were incorporated into the larger ones as the oxidation time and temperature increased. The den-sity of the smaller ones based critically lower eventually. The SOI wafers directly bonded at the room temperature were annealed at 120$0^{\circ}C$ for 1 hour. The stacking faults at the bonding and oxidation interface were examined and there were anomalies in the distributions of the stacking faults of the bonded region to arrange in ordered ring-like fashion.

• Tribology and Lubricants
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• v.16 no.4
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• pp.282-288
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• 2000

A sliding friction and wear test for silicon nitride (Si,N4) was conducted using a ball-on-disk specimen configuration. The material used in this study was HIPed silicon nitride. The tests were carried out from room temperature to 1000$^{\circ}C$ using self-mated silicon nitride couples in laboratory air. The worn surfaces were observed by SEM and the debris particles from the worn surfaces were analyzed for oxidation by XPS. The normal load was found to have a more significant influence on the friction coefficient of the silicon nitride than an elevated temperature. The specific wear rate was found to decrease along with the sliding distance. The specific wear rate at 29.4 N and 1000$^{\circ}C$ was 292 times larger than that at room temperature. The main wear mechanism from room temperature to 750$^{\circ}C$ was caused by brittle fracture whereas from 750$^{\circ}C$ to 1000$^{\circ}C$ the wear mechanism was mainly influenced by the oxidation of silicon nitride due to the increased temperature. The oxidation of silicon nitride at a high temperature was a significant factor in the wear increase.

• Journal of the Korean Society of Industry Convergence
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• v.27 no.2_2
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• pp.397-402
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• 2024

Silicon carbide materials undergo an oxidation reaction in a high-temperature oxidizing environment and show different characteristics depending on the test temperature and time. In particular, the added oxides form a secondary phase within the sintering process and exhibit different oxidation characteristics depending on the added sintering materials. Therefore, to evaluate the oxidation characteristics, the weight of the test piece and the thickness of the oxidation layer were observed, and the structure and oxidation characteristics of the material were analyzed using SEM. SEM observation showed that an oxide layer was formed on the surface of the liquid sintered silicon carbide material after it was oxidized at 1200 ℃, 1300 ℃, and 1400 ℃ for 10 hours, respectively. Then, a bending test was performed at each temperature on the test piece with the oxidation layer formed to evaluate the change in flexural strength. The strength was 466.6 MPa at 1200 ℃, 363.1 MPa at 1300 ℃, and 350.8 MPa at 1400 ℃. Al₂O₃-SiO₂ oxidized at 1200 ℃ for 10 hours showed an increase in strength of about 21.0 MPa compared to the data before the oxidation test.

• Journal of the Korean Ceramic Society
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• v.37 no.1
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• pp.96-101
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• 2000

Comparative studies on microstructure, and mechanical and anti-oxidation properties between TiN and Ti-Si-N films were performed. The Ti-Si-N films were deposited on high-speed steel and silicon wafer substrates by plasma-assisted chemcial vapor deposition(PACVD) technique. The Si addition to TiN film caused to change the microstructure such as grain size refinement, randomly multi-oriented microstructure, and nano-sized codeposition of silicon nitride in the TiN matrix. The Ti-Si-N film, contains Si content of ∼7 at.%, showed the micro-hardness value of ∼3400 HK, which was higher than the pure TiN film whose hardness was ∼1500HK. The Ti-Si(7 at.%)-N film also showed much improved anti-oxidation properties compared with those of the pure TiN film. These properties were also related to the microstructure of Ti-Si(7 at.%)-N film was formed and retarded further oxidation of the nitridelayer. These properties were also related to the microstructure of Ti-Si(7 at.%)-N film which was characterized by nano-sized precipitates of silicon nitride phase in the TiN matrix and randomly oriented grains.

• Korean Journal of Materials Research
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• v.12 no.5
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• pp.327-333
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• 2002

In order to obtain the oxidation layer for SiC MOS, the oxide layers by thermal oxidation process with dry and wet method were deposited and characterized. Deposition temperature for oxidation layer was $1100^{\circ}C$~130$0^{\circ}C$ by $O_2$ and Ar atmosphere. The oxide thickness, surface morphology, and interface characteristic of deposited oxide layers were measurement by ellipsometer, SEM, TEM, AFM, and SIMS. Thickness of oxidation layer was confirmed 50nm and 90nm to with deposition temperature at $1150^{\circ}C$ and $1200{\circ}C$ for dry 4 hours and wet 1 hour, respectively. For the high purity oxidation layer, the necessity of sacrificial oxidation which is etched for the removal of the defeats on the wafer after quickly thermal oxidation was confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.560-564
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• 2003

Thick oxide layer was fabricated by anodic reaction and complex oxidation performed by combining low temperature thermal oxidation (50$0^{\circ}C$, 1 hr at $H_2O$/O$_2$) and a RTO (rapid thermal oxidation) process (105$0^{\circ}C$, 1 min). Electrical characteristics of OPSL (oxidized porous silicon layer) were almost the same as those of thermal silicon dioxide prepared at high temperature. The leakage current through the OPSL of 20${\mu}{\textrm}{m}$ thickness was about 100 - 500 ㎀ in the range 0 V to 50 V. The average value of breakdown field was about 3.9 MV/cm. From the XPS analysis, surface and internal oxide films of OPSL prepared by complex process were confirmed completely oxidized and also the role of RTO process was important for the densification of PSL (porous silicon layer) oxidized at low temperature.