• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.121-127
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• 2008

This paper presents design and fabrication of optimized geometry structure of electrostatic inkjet head. In order to verify effect of geometry shape, we simulate electric field intensity according to the head structure. The electric field strength increases linearly with increasing height of the micro nozzle. As the nozzle diameter decreases, the electric field along the periphery of the meniscus can be more concentrated. We design and fabricate the electrostatic inkjet heads, hole type and pole type, with optimized structure. It was fabricated using thick-thermal oxidation and silicon micromachining technique such as the deep reactive ion etching (DRIE) and chemical wet etching process. It is verified experimentally that the use of the MEMS inkjet head allows a stable and sustainable micro-dripping mode of droplet ejection. A stable micro dripping mode of ejection is observed under the voltages 2.5 kV and droplet diameter is $10\;{\mu}m$.

• 소성∙가공
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• 제13권4호
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• pp.326-333
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• 2004

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as a potential application to fabricate the surface nanosctructures because of its operational versatility and simplicity. However, nanoprobe based on lithography itself is not suitable for mass production because it is time a consuming method and not economical for commercial applications. One solution is to fabricate a mold that will be used for mass production processes such as nanoimprint, PDMS casting, and others. The objective of this study is to fabricate the silicon stamper for PDMS casting process by a mastless fabrication technique using the combination of nano/micro machining by Nanoindenter XP and KOH wet etching. Effect of the Berkovich tip alignment on the deformation was investigated. Grooves were machined on a silicon surface, which has native oxide on it, by constant load scratch (CLS), and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structures was made because of the etch mask effect of the mechanically affected layer generated by nanoscratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved groove and convex structures were used as a stamper for PDMS casting process.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2009년도 추계학술발표대회 논문집
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• pp.383-387
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• 2009

Multi-crystalline silicon surface etching without grain-boundary delineation is a challenging task for the fabrication of high efficiency solar cell. The use of sodium hydroxide - sodium hypochlorite (NaOH40% + NaOCl 12%) solution for texturing multi-crystalline silicon wafer surface in solar cell fabrication line is reported in this article. in light current-voltage results, the cells etched in NaOH 40% + NaOCl 12% = 1:2 exhibited higher short circuit current and open circuit voltage than those of the cells etched in NaOH 40% + NaOCl 12% = 1:1 solution. we have obtained 15.19% conversion efficiency in large area(156cm2) multi-Si solar cells etched in NaOH 40% + NaOCl 12% = 1:1 solution.

• 한국정보통신학회논문지
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• 제4권4호
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• pp.809-815
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• 2000

The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820\mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820\mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권6호
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• pp.367-374
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• 2000

This paper presents a method to fabricate freestanding structures by (100) silicon anisotropic etching and nickel electroless plating. The electroless plating process is simpler than the electroplating, and provides good coating uniformity and improved mechanical properties. Furthermore, the (100) silicon anisotropic etching in KOH solution with being aligned to <100> direction provides vertical (100) sidewalls on etched (100) surface. In this paper, the effects of the nickel electroless plating condition on the properties of electroless plated metal structures are investigated to apply fabrication of micro structures and then various micro structures are fabricated by nickel electroless plating. And then, the structures are released by silicon anisotropic etching in KOH solution with a large gap between the structure and the substrate. The fabricated cantilever structures are $210\mum$. wide, $5\mum$. thick and $15\mum$. over the silicon substrate, and the comb structure has the comb electrodes which are $4\mum$. wide and $4.3\mum$. thick separated by$1\mum$. It is released by silicon anisotropic etching in KOH solution. The gap between the structure and the substrate is $2.5\mum$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1963-1967
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• 1996

This paper describes the analysis, design, and silicon-fabrication of a fluidic proportional amplifier, which is the most important element of fluidic logic circuits. First, FEM(finite element method) analyses were performed, using the Fluent computational fluid dynamics program, and design geometries were optimized. Then, a $40\;{\mu}m$-deep amplifier was fabricated in silicon using anisotropic dry etching.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회A
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• pp.1825-1828
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• 2008

A simple method for the fabrication of porous nano-master for antireflective surface is presented. In conventional fabrication methods for antireflective surface, coating method with low refractive index has usually been used. However, it is required to have high cost and long times for mass production. In this paper, we suggested the fabrication method of antireflective surface by the hot embossing process using the porous nano patterned master on silicon wafer fabricated by low-temperature anodic aluminum oxidation. Through multi-AAO and etching processes, nano patterned master with high aspect ratio was fabricated at the large area. Pore diameter and inter-pore distance are about 150nm and from 150 to 200nm. In order to replicate anti-reflective structure, hot embossing process was performed by varying the processing parameters such as temperature, pressure and embossing time etc. Finally, antireflective surface can be successfully obtained after etching process to remove selectively silicon layer of AAO master.

• 한국산업보건학회지
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• 제26권1호
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• pp.1-10
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• 2016

Objectives: The aim of this study is to review the results of exposure to chemicals and to extremely low frequency(ELF) magnetic fields generated in wafer fabrication operations in the semiconductor industry. Methods: Exposure assessment studies of silicon wafer fab operations in the semiconductor industry were collected through an extensive literature review of articles reported until the end of 2015. The key words used in the literature search were "semiconductor industry", "wafer fab", "silicon wafer", and "clean room," both singly and in combination. Literature reporting on airborne chemicals and extremely low frequency(ELF) magnetic fields were collected and reviewed. Results and Conclusions: Major airborne hazardous agents assessed were several organic solvents and ethylene glycol ethers from Photolithography, arsenic from ion implantation and extremely low frequency magnetic fields from the overall fabrication processes. Most exposures to chemicals reported were found to be far below permissible exposure limits(PEL) (10% < PEL). Most of these results were from operators who handled processes in a well-controlled environment. In conclusion, we found a lack of results on exposure to hazardous agents, including chemicals and radiation, which are insufficient for use in the estimation of past exposure. The results we reviewed should be applied with great caution to associate chronic health effects.

• 한국진공학회지
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• 제7권2호
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• pp.88-93
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• 1998

본 연구에서는 기계-화학적 연마(Chemical-Mechanical-Polishing: CMP)공정을 이용 하여 게이트 전극을 가지는 실리콘 전계방출 소자를 제작하였으며, 또한 그 전자방출 특성 을 분석하였다. 실리콘 전계방출 소자를 제작하기 위해 실리콘을 두단계로 이루어진 건식식 각과 산화공정으로 팁을 뾰족하게 만들었으며, 게이트를 형성하기 위하여 고 선택비를 가지 는 CMP공정을 사용하였으며, 연마 시간과 연마 압력의 변화로 게이트 높이와 개구의 직경 을 쉽게 조절할 수 있었다. 또한, CMP공정시 발생되는 디싱(dishing)문제를 산화막 마스킹 을 사용함으로 해결하여 자동 정렬된 게이트전극의 개구를 깨끗하게 형성할 수 있었다. 제 작된 에미터의 높이와 팁끝의 반경은 각각 1.1$\mu$m, 100$\AA$정도이며, 제작된 2809개의 팁 어 레이로 80V의 게이트전압에서 31$\mu$A의 방출전류를 얻을 수 있었다.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권4호
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• pp.149-154
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• 2004

This paper presents a silicon probe tip for vertical probe card application. The silicon probe tip was fabricated using MEMS technology such as porous silicon micromachining and deep- RIE (reactive ion etching). The thickness of the silicon epitaxial layers was 5 ${\mu}{\textrm}{m}$ and 7 ${\mu}{\textrm}{m}$, respectively. The width and length were 40 ${\mu}{\textrm}{m}$ and 600 ${\mu}{\textrm}{m}$, respectively. The probe structure was a multilayered structure and was composed of Au/Ni-Cr/Si$_3$N$_4$/n-epi layers. The height of the curled probe tip was measured as a function of the annealing temperature and time. Resistance characteristics of the probe tip were measured using a touchdown test.