• 한국정밀공학회지
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• 제22권2호
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• pp.194-201
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• 2005

Nanoscale fabrication of silicon substrate in an aqueous solution based on the use of atomic force microscopy was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate easily by a simple scratching process (Tribo-Nanolithography, TNL), has been applied instead of conventional silicon cantilever for scanning. A slant nanostructure can be fabricated by a process in which a thin damaged layer rapidly forms in the substrate at the diamond tip-sample junction along scanning path of the tip and simultaneously the area uncovered with the damaged layer is being etched. This study demonstrates how the TNL parameters can affect the formation of damaged layer and the shape of 3-D structure, hence introducing a new process of AFM-based nanolithography in aqueous solution.

• International Journal of Precision Engineering and Manufacturing
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• 제7권4호
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• pp.8-13
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• 2006

Nanoscale fabrication of silicon substrate in an aqueous solution based on the use of atomic force microscopy was demonstrated. A specially designed cantilever with a diamond tip, allowing the formation of a mask layer on the silicon substrate by a simple scratching process (Tribo-Nanolithography, TNL), has been applied instead of the conventional silicon cantilever for scanning. A slant nanostructure can be fabricated by a process in which a thin mask layer rapidly forms on the substrate at the diamond tip-sample junction along scanning path of the tip, and simultaneously, the area uncovered with the mask layer is etched. This study demonstrates how the TNL parameters can affect the formation of the mask layer and the shape of 3-D structure, hence introducing a new process of AFM-based nanolithography in aqueous solution.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.129-134
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• 2004

The development of fabrication processes of polycrystalline-silicon-thin-film transistors (poly-Si TFTs) at low temperatures is reviewed. Rapid crystallization through laser-induced melt-regrowth has an advantage of formation of crystalline silicon films at a low thermal budget. Solid phase crystallization techniques have also been improved for low temperature processing. Passivation of $SiO_2$/Si interface and grain boundaries is important to achieve high carrier transport properties. Oxygen plasma and $H_2O$ vapor heat treatments are proposed for effective reduction of the density of defect states. TFTs with high performance is reported.

• Transactions on Electrical and Electronic Materials
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• 제4권3호
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• pp.29-33
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• 2003

Tri-crystalline silicon wafers have three different orientations and three-grain boundaries. In this paper, tri-crystalline silicon (tri-Si) wafers have been used for the fabrication of buried contact solar cells. The optical and micro-structural properties of these cells after texturing in KOH solution have been investigated and compared with those of cast mult- crystalline silicon (multi-Si) wafers. We employed a cost effective fabrication process and achieved buried contact solar cell (BCSC) energy conversion efficiencies up to $15\%$ whereas the cast multi-Si wafer has efficiency around $14\%$.

• The Korean Journal of Ceramics
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• 제3권1호
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• pp.13-17
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• 1997

It is identified that the diamond films grown o bias-treated (100) silicon showed different surface morphologies and film textures according to the initial applied dc bias voltage at the same growth condition. The highly oriented diamond film (HODF) was successfully grown on -200 V bias-treated silicon substrate in which the heteroepitaxial relation of $(100)_{dimond}//(100)_{si}\; and\; [110]_{diamond}//[110]_{si}$ was identified. On the contrary, the heteroepitaxial relation was considerably disturbed in the samples bias-voltage was a key factor in growing the highly oriented diamond film on (100) silicon substrate. Considering the experimental results, we proposed a new model about heteroepitaxial diamond growth on silicon, in which 9 diamond unit cell are matched with 4 silicon cells and the bond covalency of both atoms is satisfied via the intermediate layer at the interface as well.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 영호남학술대회 논문집
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• pp.7-12
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• 2000

This paper presents the electrochemical etch-stop characteristics of single-crystal silicon in a tetramethyl ammonium hydroxide(TMAH):isopropyl alcohol(IPA):pyrazine solution. Addition of pyrazine to a TMAH:IPA etchant increases the etch-rate of (100) silicon, thus the elapsed time for etch-stop was shortened. The current-voltage (I-V) characteristics of n- and p-type silicon in a TMAH:IPA:pyrazine solution were obtained, respectively. Open circuit potential(OCP) and passivation potential(PP) of n- and p-type silicon, respectively, were obtained and applied potential was selected between n- and p-type silicon PP. The electrochemical etch-stop is applied to the fabrication of 801 microdiaphragms having $20{\mu}m$ thickness on a 5-inch silicon wafer. The averge thicknesses of 801 microdiaphragms fabricated on the one wafer were $20.03{\mu}m$ and standard deviation was ${\pm}0.26{\mu}m$. The silicon surface of the etch-stopped microdiaphragm was extremely flat without noticeable taper or other nonuniformities. The benefits of the electrochemical etch-stop in a TMAH:IPA:pyrazine solution become apparent when reproducibility in the microdiaphragm thickness for mass production is considered. These results indicate that the electrochemical etch-stop in a TMAH:IPA:pyrazine solution provides a powerful and versatile alternative process for fabricating high-yield silicon microdiaphragms.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.37.1-37.1
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• 2011

Miniaturization of lenses has been widely researched by various scientific and engineering techniques. As a result, micro scaled lens structure could be easily achieved from various fabrication techniques; nevertheless it is still challenging to make nano scaled lenses. This paper reports a novel fabrication method of silicon nanotemplate for nanolens array. The inverse structure of nanolens array was fabricated on silicon substrate by reactive ion etching (RIE) process. This technique has a flexibility to produce different tip shapes using different pattern masks. Once the silicon nano-tip array structure is well-defined using an optimized recipe, it is followed by polymer molding to duplicate nanolens array from the template. Finally, the nanostructures formed on silicon nanotemplate and polymer replica were investigated using FE-SEM and AFM measurements. The nano scaled lens can be manufactured from the same template, also using other replication techniques such as imprinting, injection molding and so on.

• 센서학회지
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• 제24권4호
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• pp.274-279
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• 2015

This paper describes optimizing fabrication methods for 2-axis electrically levitated MEMS gyroscope. Electrostatically levitated gyroscope has very high potential of performance due to the fact that its proof mass is not mechanically bound to any other structures, but its complex structure and difficulty of fabrication holds back the research that only a few researches have been reported. In this work, fabrication method for glass-silicon-glass 3-floor structure for 2-axis electrically levitated MEMS gyroscope is presented, including simplified multi-level glass etch method utilizing photoresist attack, preventing metal diffusion by adding middle layer of metal electrode, overcoming Deep RIE limitation by separate fabrication of silicon structures and keeping the electrode safe from dicing debris.

• Current Photovoltaic Research
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• 제2권2호
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• pp.41-47
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• 2014

Extensive investigation on silicon based thin film reveals a wide range of film characteristics, from low optical gap to high optical gap, from amorphous to micro-crystalline silicon etc. Fabrication of single junction, tandem and triple junction solar cell with suitable materials, indicate that fabrication of solar cell of a relatively moderate efficiency is possible with a better light induced stability. Due to these investigations, various competing materials like wide band gap silicon carbide and silicon oxide, low band gap micro-crystalline silicon and silicon germanium etc were also prepared and applied to the solar cells. Such a multi-junction solar cell can be a technologically promising photo-voltaic device, as the external quantum efficiency of such a cell covers a wider spectral range.

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.