• 한국주조공학회지
• /
• 제26권6호
• /
• pp.241-248
• /
• 2006

The effects of silicon content and melt treatment on the fluidity of Al-Si alloys during squeeze casting were investigated. The fluidity of Al-3.0 wt%Si alloy was found to be lower than that of Al-1.0 wt%Si and the fluidity of the alloy with more than 3.0 wt%Si increased with the silicon content upto 13.0 wt% and rather decreased with15.0 wt%. The fluidity was also increased by the separated treatment of grain refinement or eutectic modification, and even more by the simultaneous treatment of both. The fluidity of hypereutectic alloy was increased by the refinement of primary silicon particle.

• 한국재료학회지
• /
• 제16권9호
• /
• pp.571-577
• /
• 2006

We fabricated thermal evaporated 10 nm-Ni/(poly)Si and 10 nm-Ni/1 nm-Ir/(poly)Si films to investigate the thermal stability of nickel monosilicide at the elevated temperatures by rapid annealing them at the temperatures of $300{\sim}1200^{\circ}C$ for 40 seconds. Silicides for salicide process was formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester is used for sheet resistance. Scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An x-ray diffractometer and an auger depth profile scope were used for phase and composition analysis, respectively. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1200^{\circ}C$ and $800^{\circ}C$, respectively, while the conventional nickel monosilicide showed low resistance below $700^{\circ}C$. The grain boundary diffusion and agglomeration of silicides led to lower the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.

• 센서학회지
• /
• 제18권2호
• /
• pp.147-153
• /
• 2009

A thermal flow sensor has been fabricated and characterized, consisting of a center resistive heater surrounded by two upstream and one downstream temperature sensing resistors. The heater and temperature sensing resistors are fabricated from nitrogen-doped(n-type) polycrystalline silicon carbide(poly-SiC) deposited by LPCVD(low pressure chemical vapor deposition) on LPCVD silicon nitride films on a Si substrate. Cavities were etched into the Si substrate from the front side to create suspended silicon nitride membranes carrying the poly-SiC elements. One upstream sensor is located $50{\mu}m$ from the heater and has a sensitivity of $0.73{\Omega}$/sccm with ${\sim}15\;ms$ rise time in a dynamic range of 1000 sccm. N-type poly-SiC has a linear negative temperature coefficient and a TCR(temperature coefficient of resistance) of $-1.24{\times}10^{-3}/^{\circ}C$ from room temperature to $100^{\circ}C$.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
• /
• pp.202-205
• /
• 2002

The photoluminescence (PL) characteristics of the silicon-oxygen(Si-O) superlattice formed by molecular beam epitaxy (MBE) were studied. To confirm the presence of the nanocrystalline Si structure, Raman scattering measurement was performed. The blue shift was observed in the PL peak of the oxygen-annealed sample, compared to the hydrogen-annealed sample, which is due to a contribution of smaller crystallites. Our results determine the right direction for the fabrication of silicon-based optoelectronic and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in high-speed and low-power silicon MOSFET devices in the future.

• 한국표면공학회지
• /
• 제43권1호
• /
• pp.7-11
• /
• 2010

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

• 한국추진공학회지
• /
• 제23권2호
• /
• pp.68-77
• /
• 2019

고체 및 액체 로켓 추진 기관 내열부품으로 사용하기 위하여 C/SiC 복합 재료를 LSI(Liquid Silicon Infiltration) 공법으로 개발하였다. 조성비에 따른 내열 특성은 아크 플라즈마, 초음속 토치 시험으로 평가하였으며 $H_2O$ 및 $CO_2$ 산화에 의한 유효 삭마식을 제시하였다. 연소시험을 통하여 고체 및 액체 추진기관용 노즐목 삽입재, 확대부 내열재 및 연소실 내열부품 등 다양한 형상으로 제작이 가능함을 확인하였으며 높은 내삭마 성능과 열구조 성능이 입증되었다.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2012년도 춘계학술발표대회
• /
• pp.88.1-88.1
• /
• 2012

Silicon nanowires (SiNWs), due to their unusual quantum-confinement effects that lead to superior electrical and optical properties compared to those of the bulk silicon, have been widely researched as a potential building block in a variety of novel electronic devices. The conventional means for the synthesis of SiNWs has been the vapor-liquid-solid method using chemical vapor deposition; however, this method is time consuming, environmentally unfriendly, and do not support vertical growth. As an alternate, the electroless etching method has been proposed, which uses metal catalysts contained in aqueous hydrofluoric acids (HF) for vertically etching the bulk silicon substrate. This new method can support large-area growth in a short time, and vertically aligned SiNWs with high aspect ratio can be readily synthesized with excellent reproducibility. Nonetheless, there still are rooms for improvement such as the poor surface characteristics that lead to degradation in electrical performance, and non-uniformity of the diameter and shapes of the synthesized SiNWs. Here, we report a facile method of SiNWs synthesis having uniform sizes, diameters, and shapes, which may be other than just cylindrical shapes using a modified nanosphere lithography technique. The diameters of the polystyrene nanospheres can be adjustable through varying the time of O2 plasma treatment, which serve as a mask template for metal deposition on a silicon substrate. After the removal of the nanospheres, SiNWs having the exact same shape as the mask are synthesized using wet etching technique in a solution of HF, hydrogen peroxide, and deionized water. Different electrical and optical characteristics were obtained according to the shapes and sizes of the SiNWs, which implies that they can serve specific purposes according to their types.

• Journal of Electrochemical Science and Technology
• /
• 제2권3호
• /
• pp.168-173
• /
• 2011

The availability, low toxicity, and high degree of technological development make silicon the most likely material to be used in solar cells, the cost of solar cells depends entirely on cost of high purity silicon production. The present work was conducted to electrodeposite of silicon from $K_2SiF_6$, an inexpensive raw material prepared from fluorosilicic acid ($H_2SiF_6$) produced in Iraqi Fertilizer plants, and using inexpensive graphite material as cathode electrode. The preparation of potassium fluorosilicate was performed at ($60^{\circ}C$) in a three necks flask provided with a stirrer, while the electro deposition was performed at $750^{\circ}C$ in a three-electrodes configuration with melt containing in graphite pot. High purity potassium fluorosilicate (99.25%) was obtained at temperature ($60^{\circ}C$), molar ratio-KCl/$H_2SiF_6$(1.4) and agitation (600 rpm). Spongy compact deposits were obtained for silicon with purity not less than (99.97%) at cathode potential (-0.8 V vs. Pt), $K_2SiF_6$ concentration (14% mole percent) with grain size (130 ${\mu}m$) and level of impurities (Cu, Fe and Ni) less than (0.02%).

• 전기전자학회논문지
• /
• 제23권3호
• /
• pp.811-816
• /
• 2019

초고진공 화학기상증착장치(UHV-CVD)에 의해 성장된 실리콘-흡착된 산소(Si-O) 초격자가 실리콘 양자전자소자를 위한 에피택셜 장벽으로 소개되었다. 전류-전압 측정 결과 높은 브레이크다운 전압을 갖는 매우 안정하고 양호한 절연특성을 나타내었다. 에피택셜 성장된 Si-O 초격자는 SOI(silicon on insulator)를 대체할 수 있는 절연층으로도 사용될 수 있음을 보여준다. 이 두꺼운 장벽은 전계효과트랜지스터(FET)의 절연 게이트로 유용하게 사용될 수 있어 FET 위에 또 다른 FET를 제작할 수 있으므로 미래 실리콘계 3차원 집적회로의 궁극적인 목표에 한층 더 다가갈 수 있는 가능성을 보여주는 것이다.

• 한국표면공학회지
• /
• 제55권3호
• /
• pp.143-155
• /
• 2022

Ceramic oxide layers successfully were formed on the surface of cast Al alloys with high Si contents using plasma electrolytic oxidation (PEO) process in electrolytes containing Na₂SiO₃, NaOH, and additives. The microstructure of the oxide layers was systematically analyzed using scanning electron microscopy (SEM), cross-sectional transmission electron microscopy (TEM), X-ray diffraction patterns (XRD), and energy X-ray dispersive spectroscopy (EDS). XRD analysis indicated that the PEO untreated high-silicon Al alloys (i.e., 17.1 and 11.7 wt.% Si) consist of Al, Si and Al₂Cu phases whereas Al₂Cu phase selectively disappeared after PEO treatment. PEO process yielded an amorphous oxide layer with few second phases including γ-Al₂O₃ and Fe-rich phases. The corrosion behaviors of high-silicon Al alloys treated by PEO process were investigated using electrochemical impedance spectroscopy (EIS) and other electrochemical techniques (i.e., open circuit potential and polarization curve). Electroanalytical studies indicated that high-silicon Al alloys treated by PEO process have greater corrosion resistance than high-silicon alloys untreated by PEO process.