• Journal of the Institute of Electronics and Information Engineers
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• 제51권3호
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• pp.164-173
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• 2014

In underwater robotics, vision would be a key element for recognition in underwater environments. However, due to turbidity an underwater optical camera is rarely available. An underwater imaging sonar, as an alternative, delivers low quality sonar images which are not stable and accurate enough to find out natural objects by image processing. For this, artificial landmarks based on the characteristics of ultrasonic waves and their recognition method by a shape matrix transformation were proposed and were proven in Part 1. But, this is not working properly in undulating and dynamically noisy sea-bottom. To solve this, we propose a framework providing a selection phase of likelihood candidates, a selection phase for final candidates, recognition phase and tracking phase in sequence images, where a particle filter based selection mechanism to eliminate fake candidates and a mean shift based tracking algorithm are also proposed. All 4 steps are running in parallel and real-time processing. The proposed framework is flexible to add and to modify internal algorithms. A pool test and sea trial are carried out to prove the performance, and detail analysis of experimental results are done. Information is obtained from tracking phase such as relative distance, bearing will be expected to be used for control and navigation of underwater robots.

• KIPS Transactions on Computer and Communication Systems
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• 제11권1호
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• pp.35-42
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• 2022

Visible light communication (VLC) is a method of transmitting data through LED blinking and is vulnerable to eavesdropping because the illumination affects the wide range of area. IEEE standard 802.15.7 defines On-Off Keying (OOK), Variable Pulse Position Modulation (VPPM), and Color Shift Keying (CSK) as modulation. In this paper, we propose an encryption method in VPPM for secure communication. The VPPM uses an encoding method called 4B6B where 16 different outputs are represented with 6-bit. This paper extends the number of outputs to 20, to add complexity while not violating the 4B6B generation conditions. Then each entry in the extended 4B6B table is scrambled using vigenère cipher. The probability of decrypting each 6-bit data is $\frac{1}{20}$. Eavesdropper should perform $\sum\limits_{k=1}^{n}20^k$ number of different trials to decrypt the message if the number of keys is n. The proposed method can be applied to OOK of PHY II and CSK of PHY III. We further discuss the secure encoding that can be used in OOK and CSK without performance degradation.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제27권7A호
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• pp.668-675
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• 2002

This paper proposes pre-distorter combined LUT with 2ιpartition interpolation method to reduce nonlinear distortion which was caused by high PAPR and to update LUT quickly. Pre-distorted gain and phase can be found by using LUT which consisted of AM/AM and AM/PM value, and OFDM signal amplitude. The proposed 2ιpartition interpolation can accurately find predistorted gain and phase using bit shift and add component instead of increasing size of LUT which requires increasing the amount of computation. The performance of the proposed method was measured by the difference between HPA input and output characteristics by the LUT size, constellation, SER performance by the HPA, and LUT update error by the HPA characteristic changes. As a result, it is shown that when the size of the LUT is 32 and 64 for 16-QAM and 64-QAM, nonlinear distortion nearly didn't occurred.

• Journal of the Institute of Electronics and Information Engineers
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• 제50권1호
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• Korean Journal of Social Welfare
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• 제48권
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• pp.7-41
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• 2002

This paper analyses the proposals contained in the British Government Green Paper, A New Contract for Welfare: Partnership in Pensions for low paid workers and the potential of the new rules to guarantee a decent income in old age. The UK pension system is a partnership between the State(providing the basic state pension and the SERPS), employers(providing occupational pension scheme) and private pension providers(providing personal pensions). Although the system needs to change, this partnership remains the right foundation. However, the pension Green Paper proposes substantial changes to second tier pension provision in the UK. In particular, the Government plans to replace the SERPS with a new State Second Pension. According to the Green Paper, this will result in "dramatically better pension provision for those earning less than ${\pounds}9,000$ a year" and through increased payments to private pension schemes, will also provide "extra help to those on middle incomes(${\pounds}9,000-{\pounds}18,500$ a year). Therefore, it discusses the general principles inherent in the design of the British pension system and analyses the balance of these principles is represented in the Green Paper. The paper then examines how the Government's proposals protect individuals from a means-tested old age. This paper finds that the Green paper's proposals add up to reinventing a new two-stage basic pension. However, two key features of a such a basic pension package are missing- an 'adequate' level of payment and comprehensive entitlement. Because of these missing principles we argue that the Green Paper's proposals incorporate for the low paid. The income from the basic pension and the secondary pension which is so near the means-tested minimum that little is gained in retirement from a lifetime of work and contribution. Indeed, the shift away from collective provision and the emphasis on individual responsibility will reinforce this inequality, so that many poor will continue to experience poverty in later life.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.523-523
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• 2012

As the wafer geometric requirements continuously complicated and minutes in tens of nanometers, the expectation of real-time add-on sensors for in-situ plasma process monitoring is rapidly increasing. Various industry applications, utilizing plasma impedance monitor (PIM) and optical emission spectroscopy (OES), on etch end point detection, etch chemistry investigation, health monitoring, fault detection and classification, and advanced process control are good examples. However, process monitoring in semiconductor manufacturing industry requires non-invasiveness. The hypothesis behind the optical monitoring of plasma induced ion current is for the monitoring of plasma induced charging damage in non-invasive optical way. In plasma dielectric via etching, the bombardment of reactive ions on exposed conductor patterns may induce electrical current. Induced electrical charge can further flow down to device level, and accumulated charges in the consecutive plasma processes during back-end metallization can create plasma induced charging damage to shift the threshold voltage of device. As a preliminary research for the hypothesis, we performed two phases experiment to measure the plasma induced current in etch environmental condition. We fabricated electrical test circuits to convert induced current to flickering frequency of LED output, and the flickering frequency was measured by high speed optical plasma monitoring system (OPMS) in 10 kHz. Current-frequency calibration was done in offline by applying stepwise current increase while LED flickering was measured. Once the performance of the test circuits was evaluated, a metal pad for collecting ion bombardment during plasma etch condition was placed inside etch chamber, and the LED output frequency was measured in real-time. It was successful to acquire high speed optical emission data acquisition in 10 kHz. Offline measurement with the test circuitry was satisfactory, and we are continuously investigating the potential of real-time in-situ plasma induce current measurement via OPMS.

• Journal of The Korean Astronomical Society
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• 제47권2호
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• pp.43-47
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• 2014

Many advanced ground-based solar telescopes improve the spatial resolution of observation images using an adaptive optics (AO) system. As any AO correction remains only partial, it is necessary to use post-processing image reconstruction techniques such as speckle masking or shift-and-add (SAA) to reconstruct a high-spatial-resolution image from atmospherically degraded solar images. In the New Vacuum Solar Telescope (NVST), the spatial resolution in solar images is improved by frame selection and SAA. In order to overcome the burden of massive speckle data processing, we investigate the possibility of using the speckle reconstruction program in a real-time application at the telescope site. The code has been written in the C programming language and optimized for parallel processing in a multi-processor environment. We analyze the scalability of the code to identify possible bottlenecks, and we conclude that the presented code is capable of being run in real-time reconstruction applications at NVST and future large aperture solar telescopes if care is taken that the multi-processor environment has low latencies between the computation nodes.

• Journal of Practical Engineering Education
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• 제16권2호
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• pp.129-141
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• 2024

In recent times, there has been a shift towards student-centered higher education policies, leading to a growing interest among universities to improve students' learning outcomes. To aid in this endeavor, this study aims to provide guidance for University K to enhance their learning outcome management by comparing and analyzing their learning outcome indicators with those of other domestic and foreign universities. The study examined detailed measurement questions from major learning outcome measurement tools such as AHELO, NSSE, and CLA+. Upon comparison and analysis of University K's major learning outcome indicators with those of other universities, it was found that most of the indicators overlapped. However, some indicators such as student support/facilities for learning, instructor quality, and communication were absent from University K. Therefore, it is crucial to decide whether to add these indicators to the existing learning outcomes or to confirm them through other surveys. Moreover, even for the same indicator, some indicators with different measurement need to consider changing the measurement.

• Journal of Korea Multimedia Society
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• 제15권1호
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제44권2호
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• pp.127-138
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• 2007

In this paper, we propose a new X-masking scheme for utilizing logic built-in self-test The new scheme exploits the phase-shifting network which is based on the shift-and-add property of maximum length pseudorandom binary sequences(m-sequences). The phase-shifting network generates mask-patterns to multiple scan chains by appropriately shifting the m-sequence of an LFSR. The number of shifts required to generate each scan chain mask pattern can be dynamically reconfigured during a test session. An iterative simulation procedure to synthesize the phase-shifting network is proposed. Because the number of candidates for phase-shifting that can generate a scan chain mask pattern are very large, the proposed X-masking scheme reduce the hardware overhead efficiently. Experimental results demonstrate that the proposed X-masking technique requires less storage and hardware overhead with the conventional methods.