• Nuclear Engineering and Technology
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• v.5 no.1
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• pp.13-19
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• 1973

The photovoltaic and the electronvoltaic cells have been obtained by forming Sb-implanted n- on p-type and In-implanted p- on n-type silicon p-n junctions Such shallow implantations into silicon wafers due to each dopant were done by the VDH-Implanter. The two types of the silicon p-n junction for these cells have shown special features on their various characteristics to be fitted for the direct energy conversions. The results of the comparative study on both of these cells are described in this article.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.8
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• pp.587-595
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• 1998

Transient thermal analysis simulations are carried out using a modeling program to understand the human body model HBM ESD. The devices were simulated a one-dimensional device subjected to ESD stress by solving Poison's equation, the continuity equation, and heat flow equation. A ramp rise with peak ESD voltage during rise time is applied to the device under test and then discharged exponentially through the device. LDD and NMOS structures were studied to evaluate ESD performance, snap back voltages, device heating. Junction heating results in the necessity for increased electron concentration in the space charge region to carry the current by the ESD HBM circuit. The doping profile adihacent to junction determines the amount of charge density and magnitude of the electric field, potential drop, and device heating. Shallow slopes of LDD tend to collect the negative charge and higher potential drops and device heating.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• Journal of the Korea Society for Simulation
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• v.9 no.4
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• pp.51-58
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.

• ETRI Journal
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• v.19 no.4
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• pp.402-413
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• 1997

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

• Proceedings of the Korean Vacuum Society Conference
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• 2007.02a
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• pp.130-130
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• 2007

• Proceedings of the Korean Vacuum Society Conference
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• 2001.07a
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• pp.165-165
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• 2001

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.411-415
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• 1987

A $32{\times}33$ MOS-type area image sensor has been fabricated. The blooming current is reduced to 1/14 by forming +p photocell in P-well instead of a simple p-type substrate. A shallow n+ junction is made to improve the sensitivity of photodiode on short wavelength. Bootstrapping circuit technique is applied to obtain high speed dynamic shift register. The shift register operates at up to 10MHz for 7V clock.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.31-36
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• 2002

Low energy boron ions were implanted into the preamorphized and crystalline silicon substrates to form 0.2${\mu}m$ $p^+-n$ junctions. The rapid thermal annealing(RTA) was used to annihilate the crystal defects due to implantation and to activate the implanted boron ions, and the furnace annealing was employed to reflow the BPSG(bolo-phosphosilicate glass). The implantation conditions for Gepreamorphization were the energy of 45keV and the dose of 3$\times$1014cm-2. BF2 ions employed as a p-type dopant were implanted with the energy of 20keV and the dose of 2$\times$1015cm-2. The thermal conditions of RTA and furnace annealing were $1000^{\circ}C$/10sec and $850^{\circ}C$/40min, respectively. The junction depths were measured by SIMS and ASR techniques, and the 4-point probe was used to measure the sheet resistances. The electrical characteristics were analyzed via the leakage currents of the fabricated diodes. The single thermal processing with RTA produced shallow junctions of good qualities, and the thermal treatment sequence of furnace anneal and RTA yielded better junction characteristics than that of RTA and furnace anneal.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.3
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.