• ETRI Journal
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• v.41 no.5
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• pp.670-683
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• 2019

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high-density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack-up types on a printed circuit board. Each module was designed into 12- (version 1) and 14-layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high-speed signal-layers in the middle of two power planes, whereas Version 2 has a single high-speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S-parameters, eye-diagrams, and crosstalk voltages. The results show that the high-speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.683-684
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• 2016

The up-to-date high-performance DSP or FPGA employs SRIO(Serial Rapid IO) as a high-speed serial communications. SRIO is an industry standard regulated upto Ver 3.1. In this study we developed a backplane having a transmission rate to 15Gbps based on a TI DSP. The back plane icould be used to High-speed video transmission, and will be adopted to connecting multiple DSPs for scalable architecture. This paper will discuss the design constraints for a high-speed communication and multiple-core operation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.91-97
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• 2021

A microserver is a type of a computing server, in which two or more CPU nodes are implemented on a separate computing board, and a plurality of computing boards are integrated on a main board. In building a cluster system, the microserver has advantages in several points such as energy efficiency, area occupied, and ease of management compared to the existing method of mounting legacy servers in multiple racks. In addition, since the microserver uses a fast interconnection network between CPU nodes, performance improvement for data transfers is expected. The proposed microserver can mount a total of 16 computing boards with 4 CPU nodes on the main board, and uses Serial-RapidIO (SRIO) as an interconnection network. In order to analyze the performance of the proposed microserver in terms of the interconnection network which is a core performance issue of the microserver, we compare and quantify the performance of commercial microservers. As a result of the test, it showed up to about 7 times higher bandwidth improvement when transmitting data using the interconnection network. In addition, with CloudSuite benchmark programs used in actual cloud computing, maximum 60% reduction in execution time was obtained compared to commercial microservers with similar CPU performance specification.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.57-65
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• 2010

In this paper, we propose the structure of heterogeneous multiprocessor's concept, which is the structure of the new type of the robot controller, and we introduce an integrating structure method, which is distributed multiprocessor within controller using sRIO. We also perform the computer simulation with using the sRIO IP core which was designed within FPGA as the method for implementation of integrated heterogeneous multiprocessor by sRIO communication. Thus, we verify the result.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.33-41
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• 2014

This paper presents a IEEE1588 based clock synchronization technique for a sRIO (Serial RapidIO) network which is applied to a submarine system. Clock synchronization plays a key role in the success of a networked embedded system. Recently, the IEEE1588 algorithm making use of dedicated chipset has been widely used for the synchronization of various industrial applications. However, there is no chipset available for the sRIO network that can offer many advantages, such as low latency and jitter. In this paper, the IEEE1588 algorithm for a sRIO network is implemented using only software without any dedicated chipset. The proposed approach is verified with experimental setup.